Specific Blocks

The following subsections will describe the meaning of individual blocks generated by the block generator. A set of blocks (block classes) corresponds to a VHDL language construct like a declaration or statement.

• Assignments
  • Variable Assignment
  • Signal Assignment
• Attributes
  • Attribute Declaration
  • Attribute Specification
• Control Structures
  • If Statement
  • Case Statement
  • For Loop
  • While Loop
  • Next Statement
  • Exit Statement
  • Return Statement
  • Null Statement
• Generate Statements
  • If Generate Statement
  • Case Generate Statement
  • For Generate Statement
• Instantiations
  • Entity Instantiation
  • Package Instantiation
  • Function Instantiation
  • Procedure Instantiation
• Lists and Maps
  • Generic List
  • Generic Map
  • Port List
  • Port Map
  • Parameter List
  • Sensitivity List
• References
  • LibraryStatement Statement
  • Use Statement
  • Context Statement
• Reporting
  • Assert Statement
  • Report Statement
• Sequential
  • Package
  • Package Body
  • Function
  • Procedure
  • Process
• Structural
  • Block
  • Entity
  • Architecture
  • Component
  • Configuration
• Types
  • Subtype
  • Type
• Objects
  • Base Classes
  • Constants
  • File
  • Signals
  • Shared Variables
  • Variables