If Statement

EndBlock

pyVHDLParser.Blocks.Generic1.EndBlock

ThenBlock

pyVHDLParser.Blocks.Generic.SequentialBeginBlock

ElseBlock

pyVHDLParser.Blocks.Generic.SequentialBeginBlock

ExpressionBlockEndedByThen

pyVHDLParser.Blocks.BaseExpression.ExpressionBlockEndedByKeywordORClosingRoundBracket

IfConditionBlock

ElsIfConditionBlock