VHDL Language Model

The VHDL Language Model is a standalone Python package (see github.com/vhdl/pyVHDLModel).

• Concepts not defined by IEEE Std. 1076
  • Design
  • LibraryStatement
  • Sourcecode File
• Enumerations
  • Modes
  • Object Classes
• Design Units
  • Primary Units
    • Context
    • Configuration
    • Entity
    • Package
  • Secondary Units
    • Architeture
    • Package Body
• Interface Items
  • Generic Interface Item
    • GenericConstantInterfaceItem
    • GenericTypeInterfaceItem
    • GenericSubprogramInterfaceItem
    • GenericPackageInterfaceItem
  • Port Interface Item
    • PortSignalInterfaceItem
  • Parameter Interface Item
    • ParameterConstantInterfaceItem
    • ParameterVariableInterfaceItem
    • ParameterSignalInterfaceItem
    • ParameterFileInterfaceItem
• Subprogram Declarations
  • Procedure
  • Function
• Type Declarations
  • Scalar Types
    • Enumeration
    • Integer
    • Real
    • Physical
  • Composite Types
    • Array
    • Record
  • Access
  • File
  • Protected
• Object Declartions
  • Constant
  • Variable
  • Shared Variable
  • Signal
  • File
• Concurrent Statements
  • Assert
  • Signal Assignment
  • Instantiation
  • If Generate
  • Case Generate
  • For Generate
  • Procedure Call
  • Process
• Sequential Statements
  • Signal Assignment
  • Variable Assignment
  • If Statement
  • Case Statement
  • For Loop
  • While Loop
  • Report Statement
  • Assert Statement
  • Procedure Call