Test Report

Summary

8981
625 xfailed 8356 xpassed

Tests

TestDOM.py 6258356 0:36:12.352239

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd] 0:00:00.300781

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd'
libghdl processing time:  117.802 us
DOM translation time:    1486.327 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_and_multiple(test_behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd':
      Entities:
        - Name: tb_and_multiple
          File: tb_and_multiple.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test_behavioral
      Architectures:
        - Name: test_behavioral
          File: tb_and_multiple.vhd
          Position: 28:13
          Entity: tb_and_multiple
          Declared:
            - signal count_value : bit_vector(7 downto 0)
            - signal terminal_count : bit
          Hierarchy:
            - tc_gate: entity work.and_multiple
            - stumulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd] 0:00:00.357797

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd'
DOM: Error raised in libghdl.
libghdl: :36:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd] 0:00:00.230041

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 59
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 76
libghdl processing time:  134.202 us
DOM translation time:    901.416 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_03(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd':
      Entities:
        - Name: inline_03
          File: inline_03.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_03.vhd
          Position: 28:13
          Entity: inline_03
          Declared:
          Hierarchy:
            - process_1_b: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd] 0:00:00.237936

Setup

Call

[gw0] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
FATAL: An unknown or unhandled exception reached the topmost exception handler!
  Exception type:      ValueError
  Exception message:   GetIirKindOfNode: Parameter 'node' must not be 'Null_iir'.
  Caused in:           GetIirKindOfNode in file '/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Utils.py' at line 76
--------------------------------------------------------------------------------
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/cli/dom.py", line 351, in main
    app.Run()
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/cli/dom.py", line 200, in Run
    ArgParseMixin.Run(self)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyAttributes/ArgParseAttributes.py", line 297, in Run
    self._ParseArguments()
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyAttributes/ArgParseAttributes.py", line 309, in _ParseArguments
    self._RouteToHandler(args)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyAttributes/ArgParseAttributes.py", line 313, in _RouteToHandler
    args.func(self, args)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/cli/dom.py", line 275, in HandlePretty
    document = self.addFile(file, "pretty")
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/cli/dom.py", line 328, in addFile
    document = Document(filename)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/NonStandard.py", line 149, in __init__
    self.translate()
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/NonStandard.py", line 204, in translate
    architecture = Architecture.parse(libraryUnit, contextItems)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/DesignUnit.py", line 183, in parse
    return cls(architectureNode, name, entity, contextItems, declaredItems, statements)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/DesignUnit.py", line 165, in __init__
    super().__init__(identifier, entity, contextItems, declaredItems, statements)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyVHDLModel/SyntaxModel.py", line 2058, in __init__
    self._statements    = [] if statements is None else [s for s in statements]
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyVHDLModel/SyntaxModel.py", line 2058, in <listcomp>
    self._statements    = [] if statements is None else [s for s in statements]
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Translate.py", line 880, in GetConcurrentStatementsFromChainedNodes
    yield ProcessStatement.parse(statement, label, False)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/Concurrent.py", line 271, in parse
    return cls(processNode, label, declaredItems, statements, sensitivityList)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/Concurrent.py", line 250, in __init__
    super().__init__(label, declaredItems, statements, sensitivityList)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyVHDLModel/SyntaxModel.py", line 2378, in __init__
    SequentialDeclarations.__init__(self, declaredItems)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyVHDLModel/SyntaxModel.py", line 2285, in __init__
    self._declaredItems = [] if declaredItems is None else [i for i in declaredItems]
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyVHDLModel/SyntaxModel.py", line 2285, in <listcomp>
    self._declaredItems = [] if declaredItems is None else [i for i in declaredItems]
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Translate.py", line 721, in GetDeclaredItemsFromChainedNodes
    obj = Variable.parse(item)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/Object.py", line 145, in parse
    defaultExpression = GetExpressionFromNode(defaultValue)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Translate.py", line 484, in GetExpressionFromNode
    return cls.parse(node)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/Expression.py", line 503, in parse
    value = GetExpressionFromNode(nodes.Get_Associated_Expr(item))
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Translate.py", line 468, in GetExpressionFromNode
    kind = GetIirKindOfNode(node)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Utils.py", line 76, in GetIirKindOfNode
    raise ValueError("GetIirKindOfNode: Parameter 'node' must not be 'Null_iir'.")
--------------------------------------------------------------------------------
Please report this bug at GitHub: https://GitHub.com/pyTooling/pyTooling.TerminalUI/issues
--------------------------------------------------------------------------------

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd] 0:00:00.244569

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 57
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 59
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 63
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 67
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 68
libghdl processing time:  120.202 us
DOM translation time:    835.215 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_15(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd':
      Entities:
        - Name: inline_15
          File: inline_15.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_15.vhd
          Position: 28:13
          Entity: inline_15
          Declared:
          Hierarchy:
            - process_3_c: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd] 0:00:00.238599

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 91
libghdl processing time:  163.203 us
DOM translation time:    1376.824 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_10(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd':
      Entities:
        - Name: inline_10
          File: inline_10.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_10.vhd
          Position: 30:13
          Entity: inline_10
          Declared:
            - type std_ulogic_vector is array(........) of .....
            - subtype std_ulogic_word is ?????
            - signal csr_offset : std_ulogic_vector(2 downto 1)
          Hierarchy:
            - process_2_b: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd] 0:00:00.226100

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd'
DOM: Error raised in libghdl.
libghdl: :29:2: object class keyword such as 'variable' is expected
libghdl: :42:18: ':' expected after interface identifier
libghdl: :42:18: (found: an identifier)
libghdl: :42:27: ';' or ')' expected after interface
libghdl: :50:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd] 0:00:00.233344

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd'
DOM: Error raised in libghdl.
libghdl: :37:2: object class keyword such as 'variable' is expected
libghdl: :41:2: 'begin' is expected instead of "nature"
libghdl: :41:9: '<=' is expected instead of "sensor_matrix"
libghdl: :41:22: ';' expected at end of signal assignment
libghdl: :41:22: (found: 'is')
libghdl: :41:23: unexpected token 'is' in a concurrent statement list
libghdl: :45:11: '<=' is expected instead of "sensor_grid"
libghdl: :45:22: ';' expected at end of signal assignment
libghdl: :45:22: (found: ':')
libghdl: :45:23: unexpected token ':' in a concurrent statement list
libghdl: :49:11: '<=' is expected instead of "sensor_data"
libghdl: :49:22: ';' expected at end of signal assignment
libghdl: :49:22: (found: an identifier)
libghdl: :49:30: '<=' is expected instead of "sensor_grid"
libghdl: :49:41: ';' expected at end of signal assignment
libghdl: :49:41: (found: 'to')
libghdl: :49:42: unexpected token 'to' in a concurrent statement list
libghdl: :53:0: unexpected token 'begin' in a concurrent statement list
libghdl: :73:14: end label for an unlabeled declaration or statement

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd] 0:00:00.233070

Setup

Call

[gw1] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 60
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 64
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 66
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 68
FATAL: An unknown or unhandled exception reached the topmost exception handler!
  Exception type:      ValueError
  Exception message:   GetIirKindOfNode: Parameter 'node' must not be 'Null_iir'.
  Caused in:           GetIirKindOfNode in file '/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Utils.py' at line 76
--------------------------------------------------------------------------------
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/cli/dom.py", line 351, in main
    app.Run()
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/cli/dom.py", line 200, in Run
    ArgParseMixin.Run(self)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyAttributes/ArgParseAttributes.py", line 297, in Run
    self._ParseArguments()
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyAttributes/ArgParseAttributes.py", line 309, in _ParseArguments
    self._RouteToHandler(args)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyAttributes/ArgParseAttributes.py", line 313, in _RouteToHandler
    args.func(self, args)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/cli/dom.py", line 275, in HandlePretty
    document = self.addFile(file, "pretty")
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/cli/dom.py", line 328, in addFile
    document = Document(filename)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/NonStandard.py", line 149, in __init__
    self.translate()
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/NonStandard.py", line 204, in translate
    architecture = Architecture.parse(libraryUnit, contextItems)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/DesignUnit.py", line 183, in parse
    return cls(architectureNode, name, entity, contextItems, declaredItems, statements)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/DesignUnit.py", line 165, in __init__
    super().__init__(identifier, entity, contextItems, declaredItems, statements)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyVHDLModel/SyntaxModel.py", line 2058, in __init__
    self._statements    = [] if statements is None else [s for s in statements]
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyVHDLModel/SyntaxModel.py", line 2058, in <listcomp>
    self._statements    = [] if statements is None else [s for s in statements]
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Translate.py", line 880, in GetConcurrentStatementsFromChainedNodes
    yield ProcessStatement.parse(statement, label, False)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/Concurrent.py", line 271, in parse
    return cls(processNode, label, declaredItems, statements, sensitivityList)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/Concurrent.py", line 250, in __init__
    super().__init__(label, declaredItems, statements, sensitivityList)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyVHDLModel/SyntaxModel.py", line 2378, in __init__
    SequentialDeclarations.__init__(self, declaredItems)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyVHDLModel/SyntaxModel.py", line 2285, in __init__
    self._declaredItems = [] if declaredItems is None else [i for i in declaredItems]
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyVHDLModel/SyntaxModel.py", line 2285, in <listcomp>
    self._declaredItems = [] if declaredItems is None else [i for i in declaredItems]
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Translate.py", line 713, in GetDeclaredItemsFromChainedNodes
    obj = Constant.parse(item)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/Object.py", line 79, in parse
    defaultExpression = GetExpressionFromNode(defaultValue)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Translate.py", line 484, in GetExpressionFromNode
    return cls.parse(node)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/Expression.py", line 503, in parse
    value = GetExpressionFromNode(nodes.Get_Associated_Expr(item))
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Translate.py", line 468, in GetExpressionFromNode
    kind = GetIirKindOfNode(node)
  File "/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/site-packages/pyGHDL/dom/_Utils.py", line 76, in GetIirKindOfNode
    raise ValueError("GetIirKindOfNode: Parameter 'node' must not be 'Null_iir'.")
--------------------------------------------------------------------------------
Please report this bug at GitHub: https://GitHub.com/pyTooling/pyTooling.TerminalUI/issues
--------------------------------------------------------------------------------

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd] 0:00:00.237889

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd'
libghdl processing time:  127.402 us
DOM translation time:    936.117 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - byte_swap(behavior)
      Packages:
        - byte_swap_types
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd':
      Entities:
        - Name: byte_swap
          File: byte_swap.vhd
          Position: 34:7
          Generics:
          Ports:
            - input : in halfword
            - output : out halfword
          Declared:
          Statements:
          Architecures:
          - behavior
      Architectures:
        - Name: behavior
          File: byte_swap.vhd
          Position: 40:13
          Entity: byte_swap
          Declared:
          Hierarchy:
            - swap: process(...)
          Statements:
            ...
      Packages:
        - Name: byte_swap_types
          File: byte_swap.vhd
          Position: 22:8
          Declared:
          - subtype halfword is ?????
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd] 0:00:00.244460

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd'
libghdl processing time:  134.802 us
DOM translation time:    1896.834 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_coeff_ram(test_abstract)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd':
      Entities:
        - Name: tb_coeff_ram
          File: tb_coeff_ram.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test_abstract
      Architectures:
        - Name: test_abstract
          File: tb_coeff_ram.vhd
          Position: 28:13
          Entity: tb_coeff_ram
          Declared:
            - use work.coeff_ram_types.all
            - signal rd, wr : bit := 0
            - signal addr : coeff_ram_address := 0
            - signal d_in, d_out : real := 0.0
          Hierarchy:
            - dut: entity work.coeff_ram
            - stumulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd] 0:00:00.239394

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  151.703 us
DOM translation time:    1156.620 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_byte_swap(test_behavior)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd':
      Entities:
        - Name: tb_byte_swap
          File: tb_byte_swap.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test_behavior
      Architectures:
        - Name: test_behavior
          File: tb_byte_swap.vhd
          Position: 31:13
          Entity: tb_byte_swap
          Declared:
            - signal input, output : halfword
          Hierarchy:
            - dut: entity work.byte_swap
            - stumulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd] 0:00:00.237330

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 46
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 47
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 49
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 50
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 52
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 53
libghdl processing time:  107.602 us
DOM translation time:    791.614 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_13(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd':
      Entities:
        - Name: inline_13
          File: inline_13.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_13.vhd
          Position: 28:13
          Entity: inline_13
          Declared:
          Hierarchy:
            - process_3_b: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd] 0:00:00.236882

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 32
libghdl processing time:  121.102 us
DOM translation time:    839.715 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - and_multiple(behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd':
      Entities:
        - Name: and_multiple
          File: and_multiple.vhd
          Position: 20:7
          Generics:
          Ports:
            - i : in bit_vector
            - y : out bit
          Declared:
          Statements:
          Architecures:
          - behavioral
      Architectures:
        - Name: behavioral
          File: and_multiple.vhd
          Position: 26:13
          Entity: and_multiple
          Declared:
          Hierarchy:
            - and_reducer: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd] 0:00:00.241828

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd'
DOM: Error raised in libghdl.
libghdl: :32:54: missing ";" at end of type declaration
libghdl: :34:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd] 0:00:00.243061

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  205.204 us
DOM translation time:    1818.832 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - modem_controller(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd':
      Entities:
        - Name: modem_controller
          File: modem_controller.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: modem_controller.vhd
          Position: 28:13
          Entity: modem_controller
          Declared:
          Hierarchy:
            - modem_controller: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd] 0:00:00.232697

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd'
DOM: Error raised in libghdl.
libghdl: :40:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd] 0:00:00.224956

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd'
DOM: Error raised in libghdl.
libghdl: :39:4: object class keyword such as 'variable' is expected
libghdl: :51:4: object class keyword such as 'variable' is expected
libghdl: :67:4: object class keyword such as 'variable' is expected
libghdl: :71:4: 'begin' is expected instead of 'subtype'
libghdl: :71:4: unexpected token 'subtype' in a concurrent statement list
libghdl: :72:11: '<=' is expected instead of "electrical_bus"
libghdl: :72:25: ';' expected at end of signal assignment
libghdl: :72:25: (found: 'is')
libghdl: :72:26: unexpected token 'is' in a concurrent statement list
libghdl: :76:4: unexpected token 'subtype' in a concurrent statement list
libghdl: :77:4: unexpected token 'subtype' in a concurrent statement list
libghdl: :81:4: unexpected token 'type' in a concurrent statement list
libghdl: :85:13: '<=' is expected instead of "system_bus"
libghdl: :85:23: ';' expected at end of signal assignment
libghdl: :85:23: (found: ':')
libghdl: :85:24: unexpected token ':' in a concurrent statement list
libghdl: :86:13: '<=' is expected instead of "ferrari_engine"
libghdl: :86:41: ';' expected at end of signal assignment
libghdl: :86:41: (found: ':')
libghdl: :86:42: unexpected token ':' in a concurrent statement list
libghdl: :90:13: '<=' is expected instead of "bus_voltages"
libghdl: :90:25: ';' expected at end of signal assignment
libghdl: :90:25: (found: an identifier)
libghdl: :90:33: '<=' is expected instead of "bus_currents"
libghdl: :90:45: ';' expected at end of signal assignment
libghdl: :90:45: (found: an identifier)
libghdl: :91:6: '<=' is expected instead of "system_bus"
libghdl: :91:16: ';' expected at end of signal assignment
libghdl: :91:16: (found: 'to')
libghdl: :91:17: unexpected token 'to' in a concurrent statement list
libghdl: :95:2: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd] 0:00:00.230398

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd'
libghdl processing time:  94.302 us
DOM translation time:    749.113 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_08(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd':
      Entities:
        - Name: inline_08
          File: inline_08.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_08.vhd
          Position: 28:13
          Entity: inline_08
          Declared:
          Hierarchy:
            - process_2_a: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd] 0:00:00.228954

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 43
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 44
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 48
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 49
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  128.502 us
DOM translation time:    2404.743 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_12(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd':
      Entities:
        - Name: inline_12
          File: inline_12.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_12.vhd
          Position: 28:13
          Entity: inline_12
          Declared:
          Hierarchy:
            - process_3_a: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd] 0:00:00.234378

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 82
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 84
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 86
libghdl processing time:  145.403 us
DOM translation time:    983.617 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_01(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd':
      Entities:
        - Name: inline_01
          File: inline_01.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_01.vhd
          Position: 28:13
          Entity: inline_01
          Declared:
          Hierarchy:
            - block_1_a: block
            - process_1_a: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd] 0:00:00.264395

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd'
DOM: Error raised in libghdl.
libghdl: :34:2: object class keyword such as 'variable' is expected
libghdl: :36:6: 'begin' is expected instead of "bus_lines"
libghdl: :37:7: missing ";" at end of architecture
libghdl: :39:2: missing entity, architecture, package or configuration
libghdl: :41:2: missing entity, architecture, package or configuration
libghdl: :45:0: missing entity, architecture, package or configuration

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd] 0:00:00.241072

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd'
DOM: Error raised in libghdl.
libghdl: :34:2: object class keyword such as 'variable' is expected
libghdl: :36:2: 'begin' is expected instead of "terminal"
libghdl: :36:11: '<=' is expected instead of "local_bus"
libghdl: :36:20: ';' expected at end of signal assignment
libghdl: :36:20: (found: ':')
libghdl: :36:21: unexpected token ':' in a concurrent statement list
libghdl: :38:12: '<=' is expected instead of "long_bus"
libghdl: :38:20: ';' expected at end of signal assignment
libghdl: :38:20: (found: 'is')
libghdl: :38:21: unexpected token 'is' in a concurrent statement list
libghdl: :39:11: '<=' is expected instead of "remote_bus"
libghdl: :39:21: ';' expected at end of signal assignment
libghdl: :39:21: (found: ':')
libghdl: :39:22: unexpected token ':' in a concurrent statement list
libghdl: :43:0: unexpected token 'begin' in a concurrent statement list

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd] 0:00:00.254210

Setup

Call

[gw0] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
DOM: Unknown discete range kind 'Simple_Name' in for...loop statement at line 49.

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd] 0:00:00.235625

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd'
DOM: Error raised in libghdl.
libghdl: :32:38: missing ";" at end of subtype decalaration
libghdl: :34:2: object class keyword such as 'variable' is expected
libghdl: :46:4: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd] 0:00:00.240127

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 67
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 72
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  203.404 us
DOM translation time:    2899.351 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - computer(system_level)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd':
      Entities:
        - Name: computer
          File: computer.vhd
          Position: 22:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - system_level
      Architectures:
        - Name: system_level
          File: computer.vhd
          Position: 29:13
          Entity: computer
          Declared:
            - type opcodes is (........)
            - type reg_number is range 0 to 31
            - constant r0 : reg_number := 0
            - constant r1 : reg_number := 1
            - constant r2 : reg_number := 2
            - type instruction is record ..... end record
            - type word is record ..... end record
            - signal address : natural
            - signal read_word, write_word : word
            - signal mem_read, mem_write : bit := 0
            - signal mem_ready : bit := 0
          Hierarchy:
            - cpu: process(...)
            - memory: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd] 0:00:00.229386

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd'
DOM: Error raised in libghdl.
libghdl: :28:2: object class keyword such as 'variable' is expected
libghdl: :29:2: 'begin' is expected instead of "quantity"
libghdl: :29:11: '<=' is expected instead of "s"
libghdl: :29:12: ';' expected at end of signal assignment
libghdl: :29:12: (found: ':')
libghdl: :29:13: unexpected token ':' in a concurrent statement list
libghdl: :30:2: unexpected token 'constant' in a concurrent statement list
libghdl: :31:2: unexpected token 'constant' in a concurrent statement list
libghdl: :32:0: unexpected token 'begin' in a concurrent statement list
libghdl: :34:18: if/use is an AMS-VHDL statement
libghdl: :35:10: '==' is not the vhdl equality, replaced by '='
libghdl: :35:10: '==' expected after expression
libghdl: :35:10: (found: '=')
libghdl: :35:10: unexpected token '=' in a primary
libghdl: :35:9: ';' is expected instead of '='
libghdl: :35:10: unexpected token '=' in a simultaneous statement list
libghdl: :37:10: '==' is not the vhdl equality, replaced by '='
libghdl: :37:10: '==' expected after expression
libghdl: :37:10: (found: '=')
libghdl: :37:10: unexpected token '=' in a primary
libghdl: :37:9: ';' is expected instead of '='
libghdl: :37:10: unexpected token '=' in a simultaneous statement list
libghdl: :43:10: "<=" or ":=" expected instead of an identifier
libghdl: :46:8: '==' is not the vhdl equality, replaced by '='
libghdl: :46:8: '<=' is expected instead of '='
libghdl: :46:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd] 0:00:00.228776

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:25: ';' or ')' expected after interface
libghdl: :35:2: object class keyword such as 'variable' is expected
libghdl: :36:2: 'begin' is expected instead of 'signal'
libghdl: :36:2: unexpected token 'signal' in a concurrent statement list
libghdl: :38:0: unexpected token 'begin' in a concurrent statement list
libghdl: :40:15: if/use is an AMS-VHDL statement
libghdl: :41:12: '==' is not the vhdl equality, replaced by '='
libghdl: :41:12: '==' expected after expression
libghdl: :41:12: (found: '=')
libghdl: :41:12: unexpected token '=' in a primary
libghdl: :41:11: ';' is expected instead of '='
libghdl: :41:12: unexpected token '=' in a simultaneous statement list
libghdl: :43:12: '==' is not the vhdl equality, replaced by '='
libghdl: :43:12: '==' expected after expression
libghdl: :43:12: (found: '=')
libghdl: :43:12: unexpected token '=' in a primary
libghdl: :43:11: ';' is expected instead of '='
libghdl: :43:12: unexpected token '=' in a simultaneous statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd] 0:00:00.227277

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:25: interfaces must be separated by ';' (found ',')
libghdl: :33:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd] 0:00:00.241880

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd'
DOM: Error raised in libghdl.
libghdl: :23:17: ':' expected after interface identifier
libghdl: :23:17: (found: an identifier)
libghdl: :23:19: interfaces must be separated by ';' (found ',')
libghdl: :30:2: object class keyword such as 'variable' is expected
libghdl: :31:2: 'begin' is expected instead of "quantity"
libghdl: :31:11: '<=' is expected instead of "vout"
libghdl: :31:15: ';' expected at end of signal assignment
libghdl: :31:15: (found: an identifier)
libghdl: :31:23: '<=' is expected instead of "iout"
libghdl: :31:27: ';' expected at end of signal assignment
libghdl: :31:27: (found: an identifier)
libghdl: :31:36: '<=' is expected instead of "output"
libghdl: :32:11: '<=' is expected instead of "vamp1"
libghdl: :32:16: ';' expected at end of signal assignment
libghdl: :32:16: (found: ':')
libghdl: :32:17: unexpected token ':' in a concurrent statement list
libghdl: :33:11: '<=' is expected instead of "vamp2"
libghdl: :33:16: ';' expected at end of signal assignment
libghdl: :33:16: (found: ':')
libghdl: :33:17: unexpected token ':' in a concurrent statement list
libghdl: :34:11: '<=' is expected instead of "vamp3"
libghdl: :34:16: ';' expected at end of signal assignment
libghdl: :34:16: (found: ':')
libghdl: :34:17: unexpected token ':' in a concurrent statement list
libghdl: :35:11: '<=' is expected instead of "vamp4"
libghdl: :35:16: ';' expected at end of signal assignment
libghdl: :35:16: (found: ':')
libghdl: :35:17: unexpected token ':' in a concurrent statement list
libghdl: :36:2: unexpected token 'constant' in a concurrent statement list
libghdl: :38:0: unexpected token 'begin' in a concurrent statement list
libghdl: :40:8: '==' is not the vhdl equality, replaced by '='
libghdl: :41:8: '==' is not the vhdl equality, replaced by '='
libghdl: :41:8: '<=' is expected instead of '='
libghdl: :41:8: unexpected token '=' in a primary
libghdl: :42:8: '==' is not the vhdl equality, replaced by '='
libghdl: :42:8: '<=' is expected instead of '='
libghdl: :42:8: unexpected token '=' in a primary
libghdl: :43:8: '==' is not the vhdl equality, replaced by '='
libghdl: :43:8: '<=' is expected instead of '='
libghdl: :43:8: unexpected token '=' in a primary
libghdl: :45:10: '==' is not the vhdl equality, replaced by '='
libghdl: :45:10: '<=' is expected instead of '='
libghdl: :45:10: unexpected token '=' in a primary
libghdl: :46:10: '==' is not the vhdl equality, replaced by '='
libghdl: :46:10: '<=' is expected instead of '='
libghdl: :46:10: unexpected token '=' in a primary
libghdl: :47:10: '==' is not the vhdl equality, replaced by '='
libghdl: :47:10: '<=' is expected instead of '='
libghdl: :47:10: unexpected token '=' in a primary
libghdl: :48:10: '==' is not the vhdl equality, replaced by '='
libghdl: :48:10: '<=' is expected instead of '='
libghdl: :48:10: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd] 0:00:00.228520

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:23: interfaces must be separated by ';' (found ',')
libghdl: :31:18: ':' expected after interface identifier
libghdl: :31:18: (found: an identifier)
libghdl: :31:20: ';' or ')' expected after interface
libghdl: :42:18: ':' expected after interface identifier
libghdl: :42:18: (found: an identifier)
libghdl: :42:19: interfaces must be separated by ';' (found ',')
libghdl: :43:18: ':' expected after interface identifier
libghdl: :43:18: (found: an identifier)
libghdl: :43:20: ';' or ')' expected after interface

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd] 0:00:00.234483

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd'
DOM: Error raised in libghdl.
libghdl: :31:4: object class keyword such as 'variable' is expected
libghdl: :32:4: 'begin' is expected instead of 'signal'
libghdl: :32:4: unexpected token 'signal' in a concurrent statement list
libghdl: :33:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd] 0:00:00.234653

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd'
DOM: Error raised in libghdl.
libghdl: :35:2: object class keyword such as 'variable' is expected
libghdl: :38:6: 'begin' is expected instead of "databus"
libghdl: :39:7: missing ";" at end of architecture
libghdl: :43:0: missing entity, architecture, package or configuration
libghdl: :50:4: missing entity, architecture, package or configuration
libghdl: :54:2: missing entity, architecture, package or configuration
libghdl: :58:10: '==' is not the vhdl equality, replaced by '='
libghdl: :62:2: missing entity, architecture, package or configuration
libghdl: :65:2: missing entity, architecture, package or configuration
libghdl: :68:4: missing entity, architecture, package or configuration
libghdl: :70:2: missing entity, architecture, package or configuration
libghdl: :74:17: '==' is not the vhdl equality, replaced by '='
libghdl: :75:4: missing entity, architecture, package or configuration
libghdl: :75:21: '==' is not the vhdl equality, replaced by '='
libghdl: :76:4: missing entity, architecture, package or configuration
libghdl: :76:21: '==' is not the vhdl equality, replaced by '='
libghdl: :79:4: missing entity, architecture, package or configuration
libghdl: :79:21: '==' is not the vhdl equality, replaced by '='
libghdl: :80:4: missing entity, architecture, package or configuration
libghdl: :80:21: '==' is not the vhdl equality, replaced by '='
libghdl: :81:4: missing entity, architecture, package or configuration
libghdl: :81:21: '==' is not the vhdl equality, replaced by '='
libghdl: :82:4: missing entity, architecture, package or configuration
libghdl: :82:21: '==' is not the vhdl equality, replaced by '='
libghdl: :83:4: missing entity, architecture, package or configuration
libghdl: :83:21: '==' is not the vhdl equality, replaced by '='
libghdl: :85:4: missing entity, architecture, package or configuration
libghdl: :85:21: '==' is not the vhdl equality, replaced by '='
libghdl: :89:2: missing entity, architecture, package or configuration
libghdl: :92:2: missing entity, architecture, package or configuration
libghdl: :95:4: missing entity, architecture, package or configuration
libghdl: :97:2: missing entity, architecture, package or configuration
libghdl: :101:6: '==' is not the vhdl equality, replaced by '='
libghdl: :105:2: missing entity, architecture, package or configuration
libghdl: :108:2: missing entity, architecture, package or configuration
libghdl: :111:4: missing entity, architecture, package or configuration
libghdl: :113:2: missing entity, architecture, package or configuration
libghdl: :117:10: '==' is not the vhdl equality, replaced by '='
libghdl: :121:2: missing entity, architecture, package or configuration
libghdl: :124:2: missing entity, architecture, package or configuration
libghdl: :127:4: missing entity, architecture, package or configuration
libghdl: :129:2: missing entity, architecture, package or configuration
libghdl: :133:17: '==' is not the vhdl equality, replaced by '='
libghdl: :134:4: missing entity, architecture, package or configuration
libghdl: :134:21: '==' is not the vhdl equality, replaced by '='
libghdl: :138:4: missing entity, architecture, package or configuration
libghdl: :138:21: '==' is not the vhdl equality, replaced by '='
libghdl: :139:4: missing entity, architecture, package or configuration
libghdl: :139:21: '==' is not the vhdl equality, replaced by '='
libghdl: :140:4: missing entity, architecture, package or configuration
libghdl: :140:21: '==' is not the vhdl equality, replaced by '='
libghdl: :141:4: missing entity, architecture, package or configuration
libghdl: :141:21: '==' is not the vhdl equality, replaced by '='
libghdl: :142:4: missing entity, architecture, package or configuration
libghdl: :142:21: '==' is not the vhdl equality, replaced by '='
libghdl: :143:4: missing entity, architecture, package or configuration
libghdl: :143:21: '==' is not the vhdl equality, replaced by '='
libghdl: :144:4: missing entity, architecture, package or configuration
libghdl: :144:21: '==' is not the vhdl equality, replaced by '='
libghdl: :146:2: missing entity, architecture, package or configuration
libghdl: :149:2: missing entity, architecture, package or configuration
libghdl: :152:4: missing entity, architecture, package or configuration
libghdl: :153:4: missing entity, architecture, package or configuration
libghdl: :155:2: missing entity, architecture, package or configuration
libghdl: :159:12: '==' is not the vhdl equality, replaced by '='
libghdl: :163:2: missing entity, architecture, package or configuration
libghdl: :166:2: missing entity, architecture, package or configuration
libghdl: :169:4: missing entity, architecture, package or configuration
libghdl: :170:4: missing entity, architecture, package or configuration
libghdl: :172:2: missing entity, architecture, package or configuration
libghdl: :176:12: '==' is not the vhdl equality, replaced by '='
libghdl: :180:2: missing entity, architecture, package or configuration
libghdl: :183:2: missing entity, architecture, package or configuration
libghdl: :186:4: missing entity, architecture, package or configuration
libghdl: :187:4: missing entity, architecture, package or configuration
libghdl: :189:2: missing entity, architecture, package or configuration
libghdl: :193:12: '==' is not the vhdl equality, replaced by '='
libghdl: :197:2: missing entity, architecture, package or configuration
libghdl: :200:2: missing entity, architecture, package or configuration
libghdl: :203:4: missing entity, architecture, package or configuration
libghdl: :205:2: missing entity, architecture, package or configuration
libghdl: :209:6: '==' is not the vhdl equality, replaced by '='
libghdl: :213:2: missing entity, architecture, package or configuration
libghdl: :215:0: missing entity, architecture, package or configuration

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd] 0:00:00.249736

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd'
DOM: Error raised in libghdl.
libghdl: :28:4: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd] 0:00:00.235089

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd'
DOM: Error raised in libghdl.
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :32:2: 'begin' is expected instead of 'signal'
libghdl: :32:2: unexpected token 'signal' in a concurrent statement list
libghdl: :33:2: unexpected token 'signal' in a concurrent statement list
libghdl: :35:11: '<=' is expected instead of "v_in"
libghdl: :35:15: ';' expected at end of signal assignment
libghdl: :35:15: (found: ':')
libghdl: :35:16: unexpected token ':' in a concurrent statement list
libghdl: :36:2: unexpected token 'constant' in a concurrent statement list
libghdl: :37:2: unexpected token 'constant' in a concurrent statement list
libghdl: :38:2: unexpected token 'signal' in a concurrent statement list
libghdl: :40:0: unexpected token 'begin' in a concurrent statement list
libghdl: :51:14: end label for an unlabeled declaration or statement

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd] 0:00:00.226975

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd'
DOM: Error raised in libghdl.
libghdl: :28:4: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd] 0:00:00.222822

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd'
DOM: Error raised in libghdl.
libghdl: :29:4: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd] 0:00:00.246324

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd'
DOM: Error raised in libghdl.
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :40:39: if/use is an AMS-VHDL statement
libghdl: :50:9: if/use is an AMS-VHDL statement

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd] 0:00:00.254748

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd'
DOM: Error raised in libghdl.
libghdl: :38:4: object class keyword such as 'variable' is expected
libghdl: :39:4: 'begin' is expected instead of "quantity"
libghdl: :39:13: '<=' is expected instead of "vcap"
libghdl: :39:17: ';' expected at end of signal assignment
libghdl: :39:17: (found: an identifier)
libghdl: :39:25: '<=' is expected instead of "icap"
libghdl: :39:36: ';' expected at end of signal assignment
libghdl: :39:36: (found: an identifier)
libghdl: :39:45: '<=' is expected instead of "p1"
libghdl: :39:47: ';' expected at end of signal assignment
libghdl: :39:47: (found: 'to')
libghdl: :39:48: unexpected token 'to' in a concurrent statement list
libghdl: :43:2: unexpected token 'begin' in a concurrent statement list
libghdl: :47:9: '==' is not the vhdl equality, replaced by '='
libghdl: :49:10: '==' is not the vhdl equality, replaced by '='
libghdl: :49:10: '<=' is expected instead of '='
libghdl: :49:10: unexpected token '=' in a primary
libghdl: :60:4: object class keyword such as 'variable' is expected
libghdl: :61:4: 'begin' is expected instead of "terminal"
libghdl: :61:13: '<=' is expected instead of "a_bus"
libghdl: :61:18: ';' expected at end of signal assignment
libghdl: :61:18: (found: ':')
libghdl: :61:19: unexpected token ':' in a concurrent statement list
libghdl: :62:13: '<=' is expected instead of "signal_ground"
libghdl: :62:26: ';' expected at end of signal assignment
libghdl: :62:26: (found: ':')
libghdl: :62:27: unexpected token ':' in a concurrent statement list
libghdl: :66:13: '<=' is expected instead of "bus_drops"
libghdl: :66:22: ';' expected at end of signal assignment
libghdl: :66:22: (found: an identifier)
libghdl: :66:30: '<=' is expected instead of "bus_currents"
libghdl: :66:42: ';' expected at end of signal assignment
libghdl: :66:42: (found: an identifier)
libghdl: :66:51: '<=' is expected instead of "a_bus"
libghdl: :66:56: ';' expected at end of signal assignment
libghdl: :66:56: (found: 'to')
libghdl: :66:57: unexpected token 'to' in a concurrent statement list
libghdl: :70:13: '<=' is expected instead of "p1"
libghdl: :70:15: ';' expected at end of signal assignment
libghdl: :70:15: (found: ':')
libghdl: :70:16: unexpected token ':' in a concurrent statement list
libghdl: :71:13: '<=' is expected instead of "p2"
libghdl: :71:15: ';' expected at end of signal assignment
libghdl: :71:15: (found: ':')
libghdl: :71:16: unexpected token ':' in a concurrent statement list
libghdl: :73:13: '<=' is expected instead of "v"
libghdl: :73:14: ';' expected at end of signal assignment
libghdl: :73:14: (found: an identifier)
libghdl: :73:22: '<=' is expected instead of "i"
libghdl: :73:23: ';' expected at end of signal assignment
libghdl: :73:23: (found: an identifier)
libghdl: :73:32: '<=' is expected instead of "p1"
libghdl: :73:34: ';' expected at end of signal assignment
libghdl: :73:34: (found: 'to')
libghdl: :73:35: unexpected token 'to' in a concurrent statement list
libghdl: :77:4: unexpected token 'constant' in a concurrent statement list
libghdl: :78:4: unexpected token 'constant' in a concurrent statement list
libghdl: :79:4: unexpected token 'constant' in a concurrent statement list
libghdl: :80:4: unexpected token 'constant' in a concurrent statement list
libghdl: :81:4: unexpected token 'constant' in a concurrent statement list
libghdl: :85:4: unexpected token 'constant' in a concurrent statement list
libghdl: :89:2: unexpected token 'begin' in a concurrent statement list
libghdl: :93:9: '==' is not the vhdl equality, replaced by '='
libghdl: :94:9: '==' is not the vhdl equality, replaced by '='
libghdl: :94:9: '<=' is expected instead of '='
libghdl: :94:9: unexpected token '=' in a primary
libghdl: :95:9: '==' is not the vhdl equality, replaced by '='
libghdl: :95:9: '<=' is expected instead of '='
libghdl: :95:9: unexpected token '=' in a primary
libghdl: :96:9: '==' is not the vhdl equality, replaced by '='
libghdl: :96:9: '<=' is expected instead of '='
libghdl: :96:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd] 0:00:00.250777

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:20: interfaces must be separated by ';' (found ',')
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :34:36: if/use is an AMS-VHDL statement
libghdl: :35:6: '==' is not the vhdl equality, replaced by '='
libghdl: :35:6: '==' expected after expression
libghdl: :35:6: (found: '=')
libghdl: :35:6: unexpected token '=' in a primary
libghdl: :35:5: ';' is expected instead of '='
libghdl: :35:6: unexpected token '=' in a simultaneous statement list
libghdl: :37:6: '==' is not the vhdl equality, replaced by '='
libghdl: :37:6: '==' expected after expression
libghdl: :37:6: (found: '=')
libghdl: :37:6: unexpected token '=' in a primary
libghdl: :37:5: ';' is expected instead of '='
libghdl: :37:6: unexpected token '=' in a simultaneous statement list
libghdl: :40:8: '<=' is expected instead of 'on'
libghdl: :40:8: unexpected token 'on' in a primary
libghdl: :40:7: ';' expected at end of signal assignment
libghdl: :40:7: (found: 'on')
libghdl: :40:8: unexpected token 'on' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd] 0:00:00.242184

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd'
DOM: Error raised in libghdl.
libghdl: :32:37: missing ";" at end of subtype decalaration
libghdl: :33:37: missing ";" at end of subtype decalaration
libghdl: :34:4: object class keyword such as 'variable' is expected
libghdl: :35:4: 'begin' is expected instead of "terminal"
libghdl: :35:13: '<=' is expected instead of "anode"
libghdl: :35:27: ';' expected at end of signal assignment
libghdl: :35:27: (found: ':')
libghdl: :35:28: unexpected token ':' in a concurrent statement list
libghdl: :39:4: unexpected token 'subtype' in a concurrent statement list
libghdl: :40:4: unexpected token 'subtype' in a concurrent statement list
libghdl: :41:11: '<=' is expected instead of "radiant"
libghdl: :41:18: ';' expected at end of signal assignment
libghdl: :41:18: (found: 'is')
libghdl: :41:19: unexpected token 'is' in a concurrent statement list
libghdl: :42:13: '<=' is expected instead of "light_bulb"
libghdl: :42:45: ';' expected at end of signal assignment
libghdl: :42:45: (found: ':')
libghdl: :42:46: unexpected token ':' in a concurrent statement list
libghdl: :46:11: '<=' is expected instead of "electrical_vector"
libghdl: :46:28: ';' expected at end of signal assignment
libghdl: :46:28: (found: 'is')
libghdl: :46:29: unexpected token 'is' in a concurrent statement list
libghdl: :47:13: '<=' is expected instead of "a_bus"
libghdl: :47:18: ';' expected at end of signal assignment
libghdl: :47:18: (found: ':')
libghdl: :47:19: unexpected token ':' in a concurrent statement list
libghdl: :51:13: '<=' is expected instead of "light_illuminance"
libghdl: :51:30: ';' expected at end of signal assignment
libghdl: :51:30: (found: an identifier)
libghdl: :51:38: '<=' is expected instead of "light_bulb"
libghdl: :52:13: '<=' is expected instead of "led_flux"
libghdl: :52:21: ';' expected at end of signal assignment
libghdl: :52:21: (found: an identifier)
libghdl: :52:30: '<=' is expected instead of "light_emitting_diode"
libghdl: :56:13: '<=' is expected instead of "n1"
libghdl: :56:19: ';' expected at end of signal assignment
libghdl: :56:19: (found: ':')
libghdl: :56:20: unexpected token ':' in a concurrent statement list
libghdl: :60:13: '<=' is expected instead of "voltage_drop"
libghdl: :60:25: ';' expected at end of signal assignment
libghdl: :60:25: (found: an identifier)
libghdl: :61:13: '<=' is expected instead of "inductive_current"
libghdl: :61:69: ';' expected at end of signal assignment
libghdl: :61:69: (found: an identifier)
libghdl: :62:13: '<=' is expected instead of "n1"
libghdl: :62:15: ';' expected at end of signal assignment
libghdl: :62:15: (found: 'to')
libghdl: :62:16: unexpected token 'to' in a concurrent statement list
libghdl: :66:2: unexpected token 'begin' in a concurrent statement list
libghdl: :73:37: missing ";" at end of subtype decalaration
libghdl: :74:37: missing ";" at end of subtype decalaration
libghdl: :75:4: object class keyword such as 'variable' is expected
libghdl: :79:4: 'begin' is expected instead of "terminal"
libghdl: :79:13: '<=' is expected instead of "anode"
libghdl: :79:27: ';' expected at end of signal assignment
libghdl: :79:27: (found: ':')
libghdl: :79:28: unexpected token ':' in a concurrent statement list
libghdl: :83:13: '<=' is expected instead of "battery_voltage"
libghdl: :83:28: ';' expected at end of signal assignment
libghdl: :83:28: (found: an identifier)
libghdl: :83:36: '<=' is expected instead of "battery_current"
libghdl: :83:51: ';' expected at end of signal assignment
libghdl: :83:51: (found: an identifier)
libghdl: :83:60: '<=' is expected instead of "anode"
libghdl: :83:65: ';' expected at end of signal assignment
libghdl: :83:65: (found: 'to')
libghdl: :83:66: unexpected token 'to' in a concurrent statement list
libghdl: :84:13: '<=' is expected instead of "leakage_voltage"
libghdl: :84:28: ';' expected at end of signal assignment
libghdl: :84:28: (found: an identifier)
libghdl: :84:36: '<=' is expected instead of "leakage_current"
libghdl: :84:51: ';' expected at end of signal assignment
libghdl: :84:51: (found: an identifier)
libghdl: :84:60: '<=' is expected instead of "anode"
libghdl: :88:2: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd] 0:00:00.246909

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd'
DOM: Error raised in libghdl.
libghdl: :39:4: object class keyword such as 'variable' is expected
libghdl: :40:4: 'begin' is expected instead of "quantity"
libghdl: :40:13: '<=' is expected instead of "v_cap"
libghdl: :40:18: ';' expected at end of signal assignment
libghdl: :40:18: (found: an identifier)
libghdl: :40:26: '<=' is expected instead of "i_cap"
libghdl: :40:31: ';' expected at end of signal assignment
libghdl: :40:31: (found: an identifier)
libghdl: :40:40: '<=' is expected instead of "cap"
libghdl: :42:2: unexpected token 'begin' in a concurrent statement list
libghdl: :46:10: '==' is not the vhdl equality, replaced by '='
libghdl: :53:14: "<=" or ":=" expected instead of an identifier
libghdl: :65:4: object class keyword such as 'variable' is expected
libghdl: :66:4: 'begin' is expected instead of "quantity"
libghdl: :66:13: '<=' is expected instead of "v"
libghdl: :66:14: ';' expected at end of signal assignment
libghdl: :66:14: (found: an identifier)
libghdl: :66:22: '<=' is expected instead of "n"
libghdl: :67:13: '<=' is expected instead of "applied_force"
libghdl: :67:26: ';' expected at end of signal assignment
libghdl: :67:26: (found: ':')
libghdl: :67:27: unexpected token ':' in a concurrent statement list
libghdl: :68:13: '<=' is expected instead of "acceleration"
libghdl: :68:25: ';' expected at end of signal assignment
libghdl: :68:25: (found: ':')
libghdl: :68:26: unexpected token ':' in a concurrent statement list
libghdl: :70:13: '<=' is expected instead of "vx"
libghdl: :70:19: ';' expected at end of signal assignment
libghdl: :70:19: (found: ':')
libghdl: :70:20: unexpected token ':' in a concurrent statement list
libghdl: :72:2: unexpected token 'begin' in a concurrent statement list
libghdl: :74:17: '==' is not the vhdl equality, replaced by '='
libghdl: :78:18: '==' is not the vhdl equality, replaced by '='
libghdl: :78:18: '<=' is expected instead of '='
libghdl: :78:18: unexpected token '=' in a primary
libghdl: :87:12: "<=" or ":=" expected instead of an identifier
libghdl: :91:12: "<=" or ":=" expected instead of an identifier
libghdl: :103:4: object class keyword such as 'variable' is expected
libghdl: :104:4: 'begin' is expected instead of "quantity"
libghdl: :104:13: '<=' is expected instead of "v_cap"
libghdl: :104:18: ';' expected at end of signal assignment
libghdl: :104:18: (found: an identifier)
libghdl: :104:26: '<=' is expected instead of "i_cap"
libghdl: :104:31: ';' expected at end of signal assignment
libghdl: :104:31: (found: an identifier)
libghdl: :104:40: '<=' is expected instead of "cap"
libghdl: :106:2: unexpected token 'begin' in a concurrent statement list
libghdl: :108:10: '==' is not the vhdl equality, replaced by '='
libghdl: :114:12: "<=" or ":=" expected instead of an identifier
libghdl: :124:4: object class keyword such as 'variable' is expected
libghdl: :125:4: 'begin' is expected instead of "quantity"
libghdl: :125:13: '<=' is expected instead of "v_cap"
libghdl: :125:18: ';' expected at end of signal assignment
libghdl: :125:18: (found: an identifier)
libghdl: :125:26: '<=' is expected instead of "i_cap"
libghdl: :125:31: ';' expected at end of signal assignment
libghdl: :125:31: (found: an identifier)
libghdl: :125:40: '<=' is expected instead of "cap"
libghdl: :126:13: '<=' is expected instead of "charge"
libghdl: :126:19: ';' expected at end of signal assignment
libghdl: :126:19: (found: ':')
libghdl: :126:20: unexpected token ':' in a concurrent statement list
libghdl: :128:2: unexpected token 'begin' in a concurrent statement list
libghdl: :132:11: '==' is not the vhdl equality, replaced by '='
libghdl: :134:10: '==' is not the vhdl equality, replaced by '='
libghdl: :134:10: '<=' is expected instead of '='
libghdl: :134:10: unexpected token '=' in a primary
libghdl: :141:14: "<=" or ":=" expected instead of 'for'
libghdl: :141:13: missing ";" at end of statement
libghdl: :141:25: 'in' is expected instead of 'use'
libghdl: :141:25: unexpected token 'use' in a primary
libghdl: :141:25: 'loop' is expected instead of 'use'
libghdl: :141:35: "<=" or ":=" expected instead of '=>'
libghdl: :142:10: 'loop' is expected instead of 'if'
libghdl: :142:9: missing ";" at end of statement
libghdl: :142:12: primary expression expected
libghdl: :142:12: 'then' is expected here
libghdl: :142:12: (found: ';')
libghdl: :142:12: extra ';' ignored
libghdl: :143:8: 'if' is expected instead of 'process'
libghdl: :143:7: missing ";" at end of statement
libghdl: :143:8: 'end' is expected instead of 'process'
libghdl: :143:8: 'if' is expected instead of 'process'
libghdl: :143:7: missing ";" at end of statement
libghdl: :143:8: 'end' is expected instead of 'process'
libghdl: :152:4: object class keyword such as 'variable' is expected
libghdl: :153:4: 'begin' is expected instead of "quantity"
libghdl: :153:13: '<=' is expected instead of "v_cap"
libghdl: :153:18: ';' expected at end of signal assignment
libghdl: :153:18: (found: an identifier)
libghdl: :153:26: '<=' is expected instead of "i_cap"
libghdl: :153:31: ';' expected at end of signal assignment
libghdl: :153:31: (found: an identifier)
libghdl: :153:40: '<=' is expected instead of "cap"
libghdl: :154:13: '<=' is expected instead of "charge"
libghdl: :154:19: ';' expected at end of signal assignment
libghdl: :154:19: (found: ':')
libghdl: :154:20: unexpected token ':' in a concurrent statement list
libghdl: :156:2: unexpected token 'begin' in a concurrent statement list
libghdl: :158:11: '==' is not the vhdl equality, replaced by '='
libghdl: :159:10: '==' is not the vhdl equality, replaced by '='
libghdl: :159:10: '<=' is expected instead of '='
libghdl: :159:10: unexpected token '=' in a primary
libghdl: :165:12: "<=" or ":=" expected instead of 'for'
libghdl: :165:11: missing ";" at end of statement
libghdl: :165:23: 'in' is expected instead of 'use'
libghdl: :165:23: unexpected token 'use' in a primary
libghdl: :165:23: 'loop' is expected instead of 'use'
libghdl: :165:33: "<=" or ":=" expected instead of '=>'
libghdl: :166:8: 'loop' is expected instead of 'process'
libghdl: :166:7: missing ";" at end of statement
libghdl: :166:8: 'end' is expected instead of 'process'
libghdl: :175:4: object class keyword such as 'variable' is expected
libghdl: :176:4: 'begin' is expected instead of "quantity"
libghdl: :176:13: '<=' is expected instead of "v_cap"
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd] 0:00:00.247903

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd'
DOM: Error raised in libghdl.
libghdl: :42:1: object class keyword such as 'variable' is expected
libghdl: :43:1: 'begin' is expected instead of 'signal'
libghdl: :43:1: unexpected token 'signal' in a concurrent statement list
libghdl: :44:10: '<=' is expected instead of "acceleration"
libghdl: :44:32: ';' expected at end of signal assignment
libghdl: :44:32: (found: ':')
libghdl: :44:33: unexpected token ':' in a concurrent statement list
libghdl: :45:10: '<=' is expected instead of "phi_dot"
libghdl: :45:17: ';' expected at end of signal assignment
libghdl: :45:17: (found: ':')
libghdl: :45:18: unexpected token ':' in a concurrent statement list
libghdl: :46:1: unexpected token 'signal' in a concurrent statement list
libghdl: :47:1: unexpected token 'signal' in a concurrent statement list
libghdl: :48:1: unexpected token 'signal' in a concurrent statement list
libghdl: :50:0: unexpected token 'begin' in a concurrent statement list
libghdl: :51:33: if/use is an AMS-VHDL statement
libghdl: :52:9: '==' is not the vhdl equality, replaced by '='
libghdl: :52:9: '==' expected after expression
libghdl: :52:9: (found: '=')
libghdl: :52:9: unexpected token '=' in a primary
libghdl: :52:8: ';' is expected instead of '='
libghdl: :52:9: unexpected token '=' in a simultaneous statement list
libghdl: :53:10: '==' is not the vhdl equality, replaced by '='
libghdl: :53:10: '==' expected after expression
libghdl: :53:10: (found: '=')
libghdl: :53:10: unexpected token '=' in a primary
libghdl: :53:9: ';' is expected instead of '='
libghdl: :53:10: unexpected token '=' in a simultaneous statement list
libghdl: :55:6: '==' is not the vhdl equality, replaced by '='
libghdl: :55:6: '==' expected after expression
libghdl: :55:6: (found: '=')
libghdl: :55:6: unexpected token '=' in a primary
libghdl: :55:5: ';' is expected instead of '='
libghdl: :55:6: unexpected token '=' in a simultaneous statement list
libghdl: :56:10: '==' is not the vhdl equality, replaced by '='
libghdl: :56:10: '==' expected after expression
libghdl: :56:10: (found: '=')
libghdl: :56:10: unexpected token '=' in a primary
libghdl: :56:9: ';' is expected instead of '='
libghdl: :56:10: unexpected token '=' in a simultaneous statement list
libghdl: :58:6: '==' is not the vhdl equality, replaced by '='
libghdl: :58:6: '==' expected after expression
libghdl: :58:6: (found: '=')
libghdl: :58:6: unexpected token '=' in a primary
libghdl: :58:5: ';' is expected instead of '='
libghdl: :58:6: unexpected token '=' in a simultaneous statement list
libghdl: :59:10: '==' is not the vhdl equality, replaced by '='
libghdl: :59:10: '==' expected after expression
libghdl: :59:10: (found: '=')
libghdl: :59:10: unexpected token '=' in a primary
libghdl: :59:9: ';' is expected instead of '='
libghdl: :59:10: unexpected token '=' in a simultaneous statement list
libghdl: :61:20: '==' is not the vhdl equality, replaced by '='
libghdl: :61:20: '==' expected after expression
libghdl: :61:20: (found: '=')
libghdl: :61:20: unexpected token '=' in a primary
libghdl: :61:19: ';' is expected instead of '='
libghdl: :61:20: unexpected token '=' in a simultaneous statement list
libghdl: :62:11: '==' is not the vhdl equality, replaced by '='
libghdl: :62:11: '==' expected after expression
libghdl: :62:11: (found: '=')
libghdl: :62:11: unexpected token '=' in a primary
libghdl: :62:10: ';' is expected instead of '='
libghdl: :62:11: unexpected token '=' in a simultaneous statement list
libghdl: :65:14: '==' is not the vhdl equality, replaced by '='
libghdl: :65:14: '<=' is expected instead of '='
libghdl: :65:14: unexpected token '=' in a primary
libghdl: :66:9: '==' is not the vhdl equality, replaced by '='
libghdl: :66:9: '<=' is expected instead of '='
libghdl: :66:9: unexpected token '=' in a primary
libghdl: :84:7: '<=' is expected instead of 'on'
libghdl: :84:7: unexpected token 'on' in a primary
libghdl: :84:6: ';' expected at end of signal assignment
libghdl: :84:6: (found: 'on')
libghdl: :84:7: unexpected token 'on' in a concurrent statement list
libghdl: :85:7: '<=' is expected instead of 'on'
libghdl: :85:7: unexpected token 'on' in a primary
libghdl: :85:6: ';' expected at end of signal assignment
libghdl: :85:6: (found: 'on')
libghdl: :85:7: unexpected token 'on' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd] 0:00:00.247910

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:38: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "velocity"
libghdl: :33:19: ';' expected at end of signal assignment
libghdl: :33:19: (found: ':')
libghdl: :33:20: unexpected token ':' in a concurrent statement list
libghdl: :34:0: unexpected token 'begin' in a concurrent statement list
libghdl: :35:11: '==' is not the vhdl equality, replaced by '='
libghdl: :36:16: '==' is not the vhdl equality, replaced by '='
libghdl: :36:16: '<=' is expected instead of '='
libghdl: :36:16: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd] 0:00:00.247451

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd'
DOM: Error raised in libghdl.
libghdl: :31:4: object class keyword such as 'variable' is expected
libghdl: :32:4: 'begin' is expected instead of "terminal"
libghdl: :32:13: '<=' is expected instead of "r1_d1"
libghdl: :32:18: ';' expected at end of signal assignment
libghdl: :32:18: (found: ':')
libghdl: :32:19: unexpected token ':' in a concurrent statement list
libghdl: :33:10: '<=' is expected instead of "temp_in"
libghdl: :33:17: ';' expected at end of signal assignment
libghdl: :33:17: (found: ':')
libghdl: :33:18: unexpected token ':' in a concurrent statement list
libghdl: :34:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd] 0:00:00.239960

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:23: interfaces must be separated by ';' (found ',')
libghdl: :28:2: object class keyword such as 'variable' is expected
libghdl: :30:4: '==' is not the vhdl equality, replaced by '='
libghdl: :30:4: '<=' is expected instead of '='
libghdl: :30:4: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd] 0:00:00.248972

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:20: ';' or ')' expected after interface
libghdl: :33:2: object class keyword such as 'variable' is expected
libghdl: :37:8: '==' is not the vhdl equality, replaced by '='
libghdl: :37:8: '<=' is expected instead of '='
libghdl: :37:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd] 0:00:00.226641

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:23: interfaces must be separated by ';' (found ',')
libghdl: :29:2: object class keyword such as 'variable' is expected
libghdl: :31:8: '==' is not the vhdl equality, replaced by '='
libghdl: :31:8: '<=' is expected instead of '='
libghdl: :31:8: unexpected token '=' in a primary
libghdl: :32:9: '==' is not the vhdl equality, replaced by '='
libghdl: :32:9: '<=' is expected instead of '='
libghdl: :32:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd] 0:00:00.249468

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd'
DOM: Error raised in libghdl.
libghdl: :34:4: object class keyword such as 'variable' is expected
libghdl: :35:4: 'begin' is expected instead of "terminal"
libghdl: :35:13: '<=' is expected instead of "inm"
libghdl: :35:16: ';' expected at end of signal assignment
libghdl: :35:16: (found: ':')
libghdl: :35:17: unexpected token ':' in a concurrent statement list
libghdl: :36:13: '<=' is expected instead of "inp"
libghdl: :36:16: ';' expected at end of signal assignment
libghdl: :36:16: (found: ':')
libghdl: :36:17: unexpected token ':' in a concurrent statement list
libghdl: :37:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd] 0:00:00.235159

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd'
DOM: Error raised in libghdl.
libghdl: :29:1: object class keyword such as 'variable' is expected
libghdl: :30:4: 'begin' is expected instead of 'signal'
libghdl: :30:4: unexpected token 'signal' in a concurrent statement list
libghdl: :32:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd] 0:00:00.231375

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:25: ';' or ')' expected after interface
libghdl: :30:2: object class keyword such as 'variable' is expected
libghdl: :32:16: '==' is not the vhdl equality, replaced by '='
libghdl: :32:16: '<=' is expected instead of '='
libghdl: :32:16: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd] 0:00:00.230301

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:33: interfaces must be separated by ';' (found ',')
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:25: interfaces must be separated by ';' (found ',')
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "v_neg"
libghdl: :33:16: ';' expected at end of signal assignment
libghdl: :33:16: (found: an identifier)
libghdl: :33:24: '<=' is expected instead of "negative_supply"
libghdl: :34:11: '<=' is expected instead of "v_in"
libghdl: :34:15: ';' expected at end of signal assignment
libghdl: :34:15: (found: an identifier)
libghdl: :34:23: '<=' is expected instead of "plus_in"
libghdl: :34:30: ';' expected at end of signal assignment
libghdl: :34:30: (found: 'to')
libghdl: :34:31: unexpected token 'to' in a concurrent statement list
libghdl: :35:11: '<=' is expected instead of "v_out"
libghdl: :35:16: ';' expected at end of signal assignment
libghdl: :35:16: (found: an identifier)
libghdl: :35:24: '<=' is expected instead of "i_out"
libghdl: :35:29: ';' expected at end of signal assignment
libghdl: :35:29: (found: an identifier)
libghdl: :35:38: '<=' is expected instead of "output"
libghdl: :36:11: '<=' is expected instead of "v_amplified"
libghdl: :36:22: ';' expected at end of signal assignment
libghdl: :36:22: (found: ':')
libghdl: :36:23: unexpected token ':' in a concurrent statement list
libghdl: :38:0: unexpected token 'begin' in a concurrent statement list
libghdl: :40:30: if/use is an AMS-VHDL statement
libghdl: :41:16: '==' is not the vhdl equality, replaced by '='
libghdl: :41:16: '==' expected after expression
libghdl: :41:16: (found: '=')
libghdl: :41:16: unexpected token '=' in a primary
libghdl: :41:15: ';' is expected instead of '='
libghdl: :41:16: unexpected token '=' in a simultaneous statement list
libghdl: :43:16: '==' is not the vhdl equality, replaced by '='
libghdl: :43:16: '==' expected after expression
libghdl: :43:16: (found: '=')
libghdl: :43:16: unexpected token '=' in a primary
libghdl: :43:15: ';' is expected instead of '='
libghdl: :43:16: unexpected token '=' in a simultaneous statement list
libghdl: :45:16: '==' is not the vhdl equality, replaced by '='
libghdl: :45:16: '==' expected after expression
libghdl: :45:16: (found: '=')
libghdl: :45:16: unexpected token '=' in a primary
libghdl: :45:15: ';' is expected instead of '='
libghdl: :45:16: unexpected token '=' in a simultaneous statement list
libghdl: :48:8: '<=' is expected instead of 'on'
libghdl: :48:8: unexpected token 'on' in a primary
libghdl: :48:7: ';' expected at end of signal assignment
libghdl: :48:7: (found: 'on')
libghdl: :48:8: unexpected token 'on' in a concurrent statement list
libghdl: :50:8: '==' is not the vhdl equality, replaced by '='
libghdl: :50:8: '<=' is expected instead of '='
libghdl: :50:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd] 0:00:00.221104

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd'
DOM: Error raised in libghdl.
libghdl: :28:4: object class keyword such as 'variable' is expected
libghdl: :29:4: 'begin' is expected instead of "quantity"
libghdl: :29:13: '<=' is expected instead of "output"
libghdl: :29:19: ';' expected at end of signal assignment
libghdl: :29:19: (found: ':')
libghdl: :29:20: unexpected token ':' in a concurrent statement list
libghdl: :30:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd] 0:00:00.227934

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd'
DOM: Error raised in libghdl.
libghdl: :23:17: ':' expected after interface identifier
libghdl: :23:17: (found: an identifier)
libghdl: :23:19: interfaces must be separated by ';' (found ',')
libghdl: :30:2: object class keyword such as 'variable' is expected
libghdl: :32:17: '==' is not the vhdl equality, replaced by '='
libghdl: :32:17: '<=' is expected instead of '='
libghdl: :32:17: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd] 0:00:00.227314

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd'
DOM: Error raised in libghdl.
libghdl: :41:2: object class keyword such as 'variable' is expected
libghdl: :42:2: 'begin' is expected instead of "quantity"
libghdl: :42:11: '<=' is expected instead of "vds"
libghdl: :42:14: ';' expected at end of signal assignment
libghdl: :42:14: (found: an identifier)
libghdl: :42:22: '<=' is expected instead of "ids"
libghdl: :42:25: ';' expected at end of signal assignment
libghdl: :42:25: (found: an identifier)
libghdl: :42:34: '<=' is expected instead of "drain"
libghdl: :42:39: ';' expected at end of signal assignment
libghdl: :42:39: (found: 'to')
libghdl: :42:40: unexpected token 'to' in a concurrent statement list
libghdl: :43:11: '<=' is expected instead of "vsd"
libghdl: :43:14: ';' expected at end of signal assignment
libghdl: :43:14: (found: an identifier)
libghdl: :43:22: '<=' is expected instead of "source"
libghdl: :43:28: ';' expected at end of signal assignment
libghdl: :43:28: (found: 'to')
libghdl: :43:29: unexpected token 'to' in a concurrent statement list
libghdl: :44:11: '<=' is expected instead of "vgs"
libghdl: :44:14: ';' expected at end of signal assignment
libghdl: :44:14: (found: an identifier)
libghdl: :44:22: '<=' is expected instead of "gate"
libghdl: :44:26: ';' expected at end of signal assignment
libghdl: :44:26: (found: 'to')
libghdl: :44:27: unexpected token 'to' in a concurrent statement list
libghdl: :45:11: '<=' is expected instead of "vgd"
libghdl: :45:14: ';' expected at end of signal assignment
libghdl: :45:14: (found: an identifier)
libghdl: :45:22: '<=' is expected instead of "gate"
libghdl: :45:26: ';' expected at end of signal assignment
libghdl: :45:26: (found: 'to')
libghdl: :45:27: unexpected token 'to' in a concurrent statement list
libghdl: :47:0: unexpected token 'begin' in a concurrent statement list
libghdl: :51:12: if/use is an AMS-VHDL statement
libghdl: :55:14: '==' is not the vhdl equality, replaced by '='
libghdl: :55:14: '==' expected after expression
libghdl: :55:14: (found: '=')
libghdl: :55:14: unexpected token '=' in a primary
libghdl: :55:13: ';' is expected instead of '='
libghdl: :55:14: unexpected token '=' in a simultaneous statement list
libghdl: :57:14: '==' is not the vhdl equality, replaced by '='
libghdl: :57:14: '==' expected after expression
libghdl: :57:14: (found: '=')
libghdl: :57:14: unexpected token '=' in a primary
libghdl: :57:13: ';' is expected instead of '='
libghdl: :57:14: unexpected token '=' in a simultaneous statement list
libghdl: :59:14: '==' is not the vhdl equality, replaced by '='
libghdl: :59:14: '==' expected after expression
libghdl: :59:14: (found: '=')
libghdl: :59:14: unexpected token '=' in a primary
libghdl: :59:13: ';' is expected instead of '='
libghdl: :59:14: unexpected token '=' in a simultaneous statement list
libghdl: :64:14: '==' is not the vhdl equality, replaced by '='
libghdl: :64:14: '==' expected after expression
libghdl: :64:14: (found: '=')
libghdl: :64:14: unexpected token '=' in a primary
libghdl: :64:13: ';' is expected instead of '='
libghdl: :64:14: unexpected token '=' in a simultaneous statement list
libghdl: :66:14: '==' is not the vhdl equality, replaced by '='
libghdl: :66:14: '==' expected after expression
libghdl: :66:14: (found: '=')
libghdl: :66:14: unexpected token '=' in a primary
libghdl: :66:13: ';' is expected instead of '='
libghdl: :66:14: unexpected token '=' in a simultaneous statement list
libghdl: :68:14: '==' is not the vhdl equality, replaced by '='
libghdl: :68:14: '==' expected after expression
libghdl: :68:14: (found: '=')
libghdl: :68:14: unexpected token '=' in a primary
libghdl: :68:13: ';' is expected instead of '='
libghdl: :68:14: unexpected token '=' in a simultaneous statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd] 0:00:00.240901

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:20: ';' or ')' expected after interface
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:22: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "vin"
libghdl: :33:14: ';' expected at end of signal assignment
libghdl: :33:14: (found: an identifier)
libghdl: :33:22: '<=' is expected instead of "a"
libghdl: :34:0: unexpected token 'begin' in a concurrent statement list
libghdl: :44:14: end label for an unlabeled declaration or statement

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd] 0:00:00.244892

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:29: ';' or ')' expected after interface
libghdl: :34:2: object class keyword such as 'variable' is expected
libghdl: :48:8: '==' is not the vhdl equality, replaced by '='
libghdl: :48:8: '<=' is expected instead of '='
libghdl: :48:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd] 0:00:00.229544

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:22: ';' or ')' expected after interface
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:23: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :34:11: '==' is not the vhdl equality, replaced by '='
libghdl: :34:11: '<=' is expected instead of '='
libghdl: :34:11: unexpected token '=' in a primary
libghdl: :35:7: '==' is not the vhdl equality, replaced by '='
libghdl: :35:7: '<=' is expected instead of '='
libghdl: :35:7: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd] 0:00:00.234720

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:25: interfaces must be separated by ';' (found ',')
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :32:2: 'begin' is expected instead of "quantity"
libghdl: :32:11: '<=' is expected instead of "v_out"
libghdl: :32:16: ';' expected at end of signal assignment
libghdl: :32:16: (found: an identifier)
libghdl: :32:24: '<=' is expected instead of "i_out"
libghdl: :32:29: ';' expected at end of signal assignment
libghdl: :32:29: (found: an identifier)
libghdl: :32:38: '<=' is expected instead of "output"
libghdl: :33:11: '<=' is expected instead of "v_amplified"
libghdl: :33:22: ';' expected at end of signal assignment
libghdl: :33:22: (found: ':')
libghdl: :33:23: unexpected token ':' in a concurrent statement list
libghdl: :35:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:17: '==' is not the vhdl equality, replaced by '='
libghdl: :38:17: '==' is not the vhdl equality, replaced by '='
libghdl: :38:17: '<=' is expected instead of '='
libghdl: :38:17: unexpected token '=' in a primary
libghdl: :39:17: '==' is not the vhdl equality, replaced by '='
libghdl: :39:17: '<=' is expected instead of '='
libghdl: :39:17: unexpected token '=' in a primary
libghdl: :40:17: '==' is not the vhdl equality, replaced by '='
libghdl: :40:17: '<=' is expected instead of '='
libghdl: :40:17: unexpected token '=' in a primary
libghdl: :42:21: '==' is not the vhdl equality, replaced by '='
libghdl: :42:21: '<=' is expected instead of '='
libghdl: :42:21: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd] 0:00:00.224664

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd'
DOM: Error raised in libghdl.
libghdl: :33:2: object class keyword such as 'variable' is expected
libghdl: :34:2: 'begin' is expected instead of "quantity"
libghdl: :34:11: '<=' is expected instead of "v"
libghdl: :34:12: ';' expected at end of signal assignment
libghdl: :34:12: (found: an identifier)
libghdl: :34:20: '<=' is expected instead of "i"
libghdl: :34:21: ';' expected at end of signal assignment
libghdl: :34:21: (found: an identifier)
libghdl: :34:30: '<=' is expected instead of "plus"
libghdl: :34:34: ';' expected at end of signal assignment
libghdl: :34:34: (found: 'to')
libghdl: :34:35: unexpected token 'to' in a concurrent statement list
libghdl: :36:11: '<=' is expected instead of "shaft"
libghdl: :36:16: ';' expected at end of signal assignment
libghdl: :36:16: (found: ':')
libghdl: :36:17: unexpected token ':' in a concurrent statement list
libghdl: :37:11: '<=' is expected instead of "applied_torque"
libghdl: :37:25: ';' expected at end of signal assignment
libghdl: :37:25: (found: an identifier)
libghdl: :37:34: '<=' is expected instead of "shaft"
libghdl: :41:0: unexpected token 'begin' in a concurrent statement list
libghdl: :45:17: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd] 0:00:00.238047

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:26: interfaces must be separated by ';' (found ',')
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:25: ';' or ')' expected after interface
libghdl: :32:9: '==' is not the vhdl equality, replaced by '='
libghdl: :32:9: '<=' is expected instead of '='
libghdl: :32:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd] 0:00:00.233955

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd'
DOM: Error raised in libghdl.
libghdl: :22:40: missing ";" at end of subtype decalaration
libghdl: :23:40: missing ";" at end of subtype decalaration
libghdl: :25:3: object class keyword such as 'variable' is expected
libghdl: :30:3: 'end' is expected instead of 'subtype'
libghdl: :28:28: missing ";" at end of package declaration
libghdl: :31:3: missing entity, architecture, package or configuration
libghdl: :33:3: missing entity, architecture, package or configuration
libghdl: :40:2: missing entity, architecture, package or configuration
libghdl: :41:2: missing entity, architecture, package or configuration
libghdl: :45:0: missing entity, architecture, package or configuration
libghdl: :54:18: ':' expected after interface identifier
libghdl: :54:18: (found: an identifier)
libghdl: :54:33: ';' or ')' expected after interface
libghdl: :55:18: ':' expected after interface identifier
libghdl: :55:18: (found: an identifier)
libghdl: :55:33: ';' or ')' expected after interface
libghdl: :56:18: ':' expected after interface identifier
libghdl: :56:18: (found: an identifier)
libghdl: :56:39: ';' or ')' expected after interface
libghdl: :80:2: object class keyword such as 'variable' is expected
libghdl: :81:2: 'begin' is expected instead of "terminal"
libghdl: :81:11: '<=' is expected instead of "anodes_unused"
libghdl: :81:24: ';' expected at end of signal assignment
libghdl: :81:24: (found: ':')
libghdl: :81:25: unexpected token ':' in a concurrent statement list
libghdl: :82:11: '<=' is expected instead of "hour_display_source_2"
libghdl: :82:55: ';' expected at end of signal assignment
libghdl: :82:55: (found: ':')
libghdl: :82:56: unexpected token ':' in a concurrent statement list
libghdl: :83:11: '<=' is expected instead of "hour_illuminance_2"
libghdl: :83:29: ';' expected at end of signal assignment
libghdl: :83:29: (found: an identifier)
libghdl: :83:37: '<=' is expected instead of "hour_display_source_2"
libghdl: :84:11: '<=' is expected instead of "hour_illuminance_3"
libghdl: :84:29: ';' expected at end of signal assignment
libghdl: :84:29: (found: an identifier)
libghdl: :84:37: '<=' is expected instead of "hour_display_source_3"
libghdl: :85:11: '<=' is expected instead of "illuminances_unused"
libghdl: :85:30: ';' expected at end of signal assignment
libghdl: :85:30: (found: ':')
libghdl: :85:31: unexpected token ':' in a concurrent statement list
libghdl: :89:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd] 0:00:00.256714

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:21: interfaces must be separated by ';' (found ',')
libghdl: :35:2: object class keyword such as 'variable' is expected
libghdl: :52:4: '==' is not the vhdl equality, replaced by '='
libghdl: :52:4: '<=' is expected instead of '='
libghdl: :52:4: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd] 0:00:00.231983

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd'
DOM: Error raised in libghdl.
libghdl: :30:4: object class keyword such as 'variable' is expected
libghdl: :31:4: 'begin' is expected instead of 'signal'
libghdl: :31:4: unexpected token 'signal' in a concurrent statement list
libghdl: :32:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd] 0:00:00.234965

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:21: interfaces must be separated by ';' (found ',')
libghdl: :35:2: object class keyword such as 'variable' is expected
libghdl: :36:2: 'begin' is expected instead of "limit"
libghdl: :36:8: '<=' is expected instead of "v"
libghdl: :36:9: ';' expected at end of signal assignment
libghdl: :36:9: (found: ':')
libghdl: :36:10: unexpected token ':' in a concurrent statement list
libghdl: :38:0: unexpected token 'begin' in a concurrent statement list
libghdl: :52:4: '==' is not the vhdl equality, replaced by '='
libghdl: :52:4: '<=' is expected instead of '='
libghdl: :52:4: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd] 0:00:00.230817

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd'
DOM: Error raised in libghdl.
libghdl: :36:2: object class keyword such as 'variable' is expected
libghdl: :37:2: 'begin' is expected instead of "quantity"
libghdl: :37:11: '<=' is expected instead of "current_length"
libghdl: :37:25: ';' expected at end of signal assignment
libghdl: :37:25: (found: ':')
libghdl: :37:26: unexpected token ':' in a concurrent statement list
libghdl: :39:0: unexpected token 'begin' in a concurrent statement list
libghdl: :41:26: if/use is an AMS-VHDL statement
libghdl: :42:19: '==' is not the vhdl equality, replaced by '='
libghdl: :42:19: '==' expected after expression
libghdl: :42:19: (found: '=')
libghdl: :42:19: unexpected token '=' in a primary
libghdl: :42:18: ';' is expected instead of '='
libghdl: :42:19: unexpected token '=' in a simultaneous statement list
libghdl: :44:19: '==' is not the vhdl equality, replaced by '='
libghdl: :44:19: '==' expected after expression
libghdl: :44:19: (found: '=')
libghdl: :44:19: unexpected token '=' in a primary
libghdl: :44:18: ';' is expected instead of '='
libghdl: :44:19: unexpected token '=' in a simultaneous statement list
libghdl: :47:8: '<=' is expected instead of "phi"
libghdl: :47:15: ';' expected at end of signal assignment
libghdl: :47:15: (found: '=>')
libghdl: :47:16: unexpected token '=>' in a concurrent statement list
libghdl: :50:8: '<=' is expected instead of "phi"
libghdl: :50:15: ';' expected at end of signal assignment
libghdl: :50:15: (found: '=>')
libghdl: :50:16: unexpected token '=>' in a concurrent statement list
libghdl: :54:4: '==' is not the vhdl equality, replaced by '='
libghdl: :54:4: '<=' is expected instead of '='
libghdl: :54:4: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd] 0:00:00.251594

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd'
DOM: Error raised in libghdl.
libghdl: :27:2: object class keyword such as 'variable' is expected
libghdl: :28:2: 'begin' is expected instead of 'constant'
libghdl: :28:2: unexpected token 'constant' in a concurrent statement list
libghdl: :30:2: unexpected token 'subtype' in a concurrent statement list
libghdl: :34:2: unexpected token 'subtype' in a concurrent statement list
libghdl: :35:11: '<=' is expected instead of "capacitor_charge"
libghdl: :35:27: ';' expected at end of signal assignment
libghdl: :35:27: (found: ':')
libghdl: :35:28: unexpected token ':' in a concurrent statement list
libghdl: :39:11: '<=' is expected instead of "engine_power"
libghdl: :39:23: ';' expected at end of signal assignment
libghdl: :39:23: (found: ':')
libghdl: :39:24: unexpected token ':' in a concurrent statement list
libghdl: :43:11: '<=' is expected instead of "i_sense"
libghdl: :43:18: ';' expected at end of signal assignment
libghdl: :43:18: (found: ':')
libghdl: :43:19: unexpected token ':' in a concurrent statement list
libghdl: :47:11: '<=' is expected instead of "amplifier_gains"
libghdl: :47:26: ';' expected at end of signal assignment
libghdl: :47:26: (found: ':')
libghdl: :47:27: unexpected token ':' in a concurrent statement list
libghdl: :51:0: unexpected token 'begin' in a concurrent statement list
libghdl: :55:19: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd] 0:00:00.234941

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd'
DOM: Error raised in libghdl.
libghdl: :30:4: object class keyword such as 'variable' is expected
libghdl: :31:1: 'begin' is expected instead of "terminal"
libghdl: :31:10: '<=' is expected instead of "in_switch"
libghdl: :31:19: ';' expected at end of signal assignment
libghdl: :31:19: (found: ':')
libghdl: :31:20: unexpected token ':' in a concurrent statement list
libghdl: :32:4: unexpected token 'signal' in a concurrent statement list
libghdl: :33:0: unexpected token 'begin' in a concurrent statement list
libghdl: :46:26: space is required between number and unit name

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd] 0:00:00.241007

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd'
DOM: Error raised in libghdl.
libghdl: :29:2: object class keyword such as 'variable' is expected
libghdl: :30:2: 'begin' is expected instead of "quantity"
libghdl: :30:11: '<=' is expected instead of "v"
libghdl: :30:12: ';' expected at end of signal assignment
libghdl: :30:12: (found: an identifier)
libghdl: :30:20: '<=' is expected instead of "i"
libghdl: :30:21: ';' expected at end of signal assignment
libghdl: :30:21: (found: an identifier)
libghdl: :30:30: '<=' is expected instead of "p"
libghdl: :31:2: unexpected token 'constant' in a concurrent statement list
libghdl: :33:2: unexpected token 'type' in a concurrent statement list
libghdl: :34:2: unexpected token 'constant' in a concurrent statement list
libghdl: :36:0: unexpected token 'begin' in a concurrent statement list
libghdl: :40:27: if/use is an AMS-VHDL statement
libghdl: :41:6: '==' is not the vhdl equality, replaced by '='
libghdl: :41:6: '==' expected after expression
libghdl: :41:6: (found: '=')
libghdl: :41:6: unexpected token '=' in a primary
libghdl: :41:5: ';' is expected instead of '='
libghdl: :41:6: unexpected token '=' in a simultaneous statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd] 0:00:00.230934

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd'
DOM: Error raised in libghdl.
libghdl: :32:4: object class keyword such as 'variable' is expected
libghdl: :33:4: 'begin' is expected instead of "quantity"
libghdl: :33:13: '<=' is expected instead of "amplified_input1"
libghdl: :33:47: ';' expected at end of signal assignment
libghdl: :33:47: (found: ':')
libghdl: :33:48: unexpected token ':' in a concurrent statement list
libghdl: :35:4: unexpected token 'constant' in a concurrent statement list
libghdl: :36:4: unexpected token 'constant' in a concurrent statement list
libghdl: :40:2: unexpected token 'begin' in a concurrent statement list
libghdl: :44:21: '==' is not the vhdl equality, replaced by '='
libghdl: :45:21: '==' is not the vhdl equality, replaced by '='
libghdl: :45:21: '<=' is expected instead of '='
libghdl: :45:21: unexpected token '=' in a primary
libghdl: :46:11: '==' is not the vhdl equality, replaced by '='
libghdl: :46:11: '<=' is expected instead of '='
libghdl: :46:11: unexpected token '=' in a primary
libghdl: :55:4: object class keyword such as 'variable' is expected
libghdl: :57:4: 'begin' is expected instead of 'constant'
libghdl: :57:4: unexpected token 'constant' in a concurrent statement list
libghdl: :58:4: unexpected token 'constant' in a concurrent statement list
libghdl: :60:2: unexpected token 'begin' in a concurrent statement list
libghdl: :64:11: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd] 0:00:00.234640

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd'
DOM: Error raised in libghdl.
libghdl: :30:4: object class keyword such as 'variable' is expected
libghdl: :31:4: 'begin' is expected instead of 'signal'
libghdl: :31:4: unexpected token 'signal' in a concurrent statement list
libghdl: :32:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd] 0:00:00.237072

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd'
DOM: Error raised in libghdl.
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :32:2: 'begin' is expected instead of "quantity"
libghdl: :32:11: '<=' is expected instead of "v_in"
libghdl: :32:15: ';' expected at end of signal assignment
libghdl: :32:15: (found: an identifier)
libghdl: :32:23: '<=' is expected instead of "input"
libghdl: :33:11: '<=' is expected instead of "v_amplified"
libghdl: :33:22: ';' expected at end of signal assignment
libghdl: :33:22: (found: ':')
libghdl: :33:23: unexpected token ':' in a concurrent statement list
libghdl: :34:2: unexpected token 'constant' in a concurrent statement list
libghdl: :36:2: unexpected token 'constant' in a concurrent statement list
libghdl: :37:2: unexpected token 'constant' in a concurrent statement list
libghdl: :38:11: '<=' is expected instead of "gate"
libghdl: :38:30: ';' expected at end of signal assignment
libghdl: :38:30: (found: ':')
libghdl: :38:31: unexpected token ':' in a concurrent statement list
libghdl: :39:11: '<=' is expected instead of "vds"
libghdl: :39:14: ';' expected at end of signal assignment
libghdl: :39:14: (found: an identifier)
libghdl: :39:22: '<=' is expected instead of "ids"
libghdl: :39:25: ';' expected at end of signal assignment
libghdl: :39:25: (found: an identifier)
libghdl: :39:34: '<=' is expected instead of "drain"
libghdl: :39:39: ';' expected at end of signal assignment
libghdl: :39:39: (found: 'to')
libghdl: :39:40: unexpected token 'to' in a concurrent statement list
libghdl: :40:11: '<=' is expected instead of "vsd"
libghdl: :40:14: ';' expected at end of signal assignment
libghdl: :40:14: (found: an identifier)
libghdl: :40:22: '<=' is expected instead of "source"
libghdl: :40:28: ';' expected at end of signal assignment
libghdl: :40:28: (found: 'to')
libghdl: :40:29: unexpected token 'to' in a concurrent statement list
libghdl: :41:11: '<=' is expected instead of "vgs"
libghdl: :41:14: ';' expected at end of signal assignment
libghdl: :41:14: (found: an identifier)
libghdl: :41:22: '<=' is expected instead of "gate"
libghdl: :41:26: ';' expected at end of signal assignment
libghdl: :41:26: (found: 'to')
libghdl: :41:27: unexpected token 'to' in a concurrent statement list
libghdl: :42:11: '<=' is expected instead of "vgd"
libghdl: :42:14: ';' expected at end of signal assignment
libghdl: :42:14: (found: an identifier)
libghdl: :42:22: '<=' is expected instead of "gate"
libghdl: :42:26: ';' expected at end of signal assignment
libghdl: :42:26: (found: 'to')
libghdl: :42:27: unexpected token 'to' in a concurrent statement list
libghdl: :44:2: unexpected token 'constant' in a concurrent statement list
libghdl: :45:2: unexpected token 'constant' in a concurrent statement list
libghdl: :46:2: unexpected token 'constant' in a concurrent statement list
libghdl: :47:11: '<=' is expected instead of "cap"
libghdl: :47:27: ';' expected at end of signal assignment
libghdl: :47:27: (found: ':')
libghdl: :47:28: unexpected token ':' in a concurrent statement list
libghdl: :48:11: '<=' is expected instead of "v_plus"
libghdl: :48:17: ';' expected at end of signal assignment
libghdl: :48:17: (found: ':=')
libghdl: :48:18: unexpected token ':=' in a concurrent statement list
libghdl: :49:11: '<=' is expected instead of "v_minus"
libghdl: :49:18: ';' expected at end of signal assignment
libghdl: :49:18: (found: ':=')
libghdl: :49:19: unexpected token ':=' in a concurrent statement list
libghdl: :50:11: '<=' is expected instead of "v_cap"
libghdl: :50:16: ';' expected at end of signal assignment
libghdl: :50:16: (found: an identifier)
libghdl: :50:24: '<=' is expected instead of "cap"
libghdl: :51:11: '<=' is expected instead of "i_charge"
libghdl: :51:19: ';' expected at end of signal assignment
libghdl: :51:19: (found: an identifier)
libghdl: :51:28: '<=' is expected instead of "plus"
libghdl: :51:32: ';' expected at end of signal assignment
libghdl: :51:32: (found: 'to')
libghdl: :51:33: unexpected token 'to' in a concurrent statement list
libghdl: :52:11: '<=' is expected instead of "i_discharge"
libghdl: :52:22: ';' expected at end of signal assignment
libghdl: :52:22: (found: an identifier)
libghdl: :52:31: '<=' is expected instead of "cap"
libghdl: :52:34: ';' expected at end of signal assignment
libghdl: :52:34: (found: 'to')
libghdl: :52:35: unexpected token 'to' in a concurrent statement list
libghdl: :54:0: unexpected token 'begin' in a concurrent statement list
libghdl: :58:25: if/use is an AMS-VHDL statement
libghdl: :59:16: '==' is not the vhdl equality, replaced by '='
libghdl: :59:16: '==' expected after expression
libghdl: :59:16: (found: '=')
libghdl: :59:16: unexpected token '=' in a primary
libghdl: :59:15: ';' is expected instead of '='
libghdl: :59:16: unexpected token '=' in a simultaneous statement list
libghdl: :61:16: '==' is not the vhdl equality, replaced by '='
libghdl: :61:16: '==' expected after expression
libghdl: :61:16: (found: '=')
libghdl: :61:16: unexpected token '=' in a primary
libghdl: :61:15: ';' is expected instead of '='
libghdl: :61:16: unexpected token '=' in a simultaneous statement list
libghdl: :63:16: '==' is not the vhdl equality, replaced by '='
libghdl: :63:16: '==' expected after expression
libghdl: :63:16: (found: '=')
libghdl: :63:16: unexpected token '=' in a primary
libghdl: :63:15: ';' is expected instead of '='
libghdl: :63:16: unexpected token '=' in a simultaneous statement list
libghdl: :68:20: if/use is an AMS-VHDL statement
libghdl: :70:10: '==' is not the vhdl equality, replaced by '='
libghdl: :70:10: '==' expected after expression
libghdl: :70:10: (found: '=')
libghdl: :70:10: unexpected token '=' in a primary
libghdl: :70:9: ';' is expected instead of '='
libghdl: :70:10: unexpected token '=' in a simultaneous statement list
libghdl: :72:10: '==' is not the vhdl equality, replaced by '='
libghdl: :72:10: '==' expected after expression
libghdl: :72:10: (found: '=')
libghdl: :72:10: unexpected token '=' in a primary
libghdl: :72:9: ';' is expected instead of '='
libghdl: :72:10: unexpected token '=' in a simultaneous statement list
libghdl: :74:10: '==' is not the vhdl equality, replaced by '='
libghdl: :74:10: '==' expected after expression
libghdl: :74:10: (found: '=')
libghdl: :74:10: unexpected token '=' in a primary
libghdl: :74:9: ';' is expected instead of '='
libghdl: :74:10: unexpected token '=' in a simultaneous statement list
libghdl: :78:10: '==' is not the vhdl equality, replaced by '='
libghdl: :78:10: '==' expected after expression
libghdl: :78:10: (found: '=')
libghdl: :78:10: unexpected token '=' in a primary
libghdl: :78:9: ';' is expected instead of '='
libghdl: :78:10: unexpected token '=' in a simultaneous statement list
libghdl: :80:10: '==' is not the vhdl equality, replaced by '='
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd] 0:00:00.242324

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:25: interfaces must be separated by ';' (found ',')
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :32:2: 'begin' is expected instead of "quantity"
libghdl: :32:11: '<=' is expected instead of "v_out"
libghdl: :32:16: ';' expected at end of signal assignment
libghdl: :32:16: (found: an identifier)
libghdl: :32:24: '<=' is expected instead of "i_out"
libghdl: :32:29: ';' expected at end of signal assignment
libghdl: :32:29: (found: an identifier)
libghdl: :32:38: '<=' is expected instead of "output"
libghdl: :33:11: '<=' is expected instead of "v_amplified"
libghdl: :33:22: ';' expected at end of signal assignment
libghdl: :33:22: (found: ':')
libghdl: :33:23: unexpected token ':' in a concurrent statement list
libghdl: :35:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:14: '==' is not the vhdl equality, replaced by '='
libghdl: :39:8: '==' is not the vhdl equality, replaced by '='
libghdl: :39:8: '<=' is expected instead of '='
libghdl: :39:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd] 0:00:00.242055

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd'
DOM: Error raised in libghdl.
libghdl: :24:1: object class keyword such as 'variable' is expected
libghdl: :25:1: 'begin' is expected instead of "quantity"
libghdl: :25:10: '<=' is expected instead of "s"
libghdl: :25:11: ';' expected at end of signal assignment
libghdl: :25:11: (found: ':')
libghdl: :25:11: unexpected token ':' in a concurrent statement list
libghdl: :26:1: unexpected token 'constant' in a concurrent statement list
libghdl: :27:1: unexpected token 'constant' in a concurrent statement list
libghdl: :28:1: unexpected token 'signal' in a concurrent statement list
libghdl: :29:1: unexpected token 'signal' in a concurrent statement list
libghdl: :30:1: unexpected token 'signal' in a concurrent statement list
libghdl: :31:0: unexpected token 'begin' in a concurrent statement list
libghdl: :32:30: if/use is an AMS-VHDL statement
libghdl: :33:4: '==' is not the vhdl equality, replaced by '='
libghdl: :33:4: '==' expected after expression
libghdl: :33:4: (found: '=')
libghdl: :33:4: unexpected token '=' in a primary
libghdl: :33:3: ';' is expected instead of '='
libghdl: :33:4: unexpected token '=' in a simultaneous statement list
libghdl: :34:4: '==' is not the vhdl equality, replaced by '='
libghdl: :34:4: '==' expected after expression
libghdl: :34:4: (found: '=')
libghdl: :34:4: unexpected token '=' in a primary
libghdl: :34:3: ';' is expected instead of '='
libghdl: :34:4: unexpected token '=' in a simultaneous statement list
libghdl: :36:4: '==' is not the vhdl equality, replaced by '='
libghdl: :36:4: '==' expected after expression
libghdl: :36:4: (found: '=')
libghdl: :36:4: unexpected token '=' in a primary
libghdl: :36:3: ';' is expected instead of '='
libghdl: :36:4: unexpected token '=' in a simultaneous statement list
libghdl: :37:4: '==' is not the vhdl equality, replaced by '='
libghdl: :37:4: '==' expected after expression
libghdl: :37:4: (found: '=')
libghdl: :37:4: unexpected token '=' in a primary
libghdl: :37:3: ';' is expected instead of '='
libghdl: :37:4: unexpected token '=' in a simultaneous statement list
libghdl: :39:8: '==' is not the vhdl equality, replaced by '='
libghdl: :39:8: '==' expected after expression
libghdl: :39:8: (found: '=')
libghdl: :39:8: unexpected token '=' in a primary
libghdl: :39:7: ';' is expected instead of '='
libghdl: :39:8: unexpected token '=' in a simultaneous statement list
libghdl: :40:8: '==' is not the vhdl equality, replaced by '='
libghdl: :40:8: '==' expected after expression
libghdl: :40:8: (found: '=')
libghdl: :40:8: unexpected token '=' in a primary
libghdl: :40:7: ';' is expected instead of '='
libghdl: :40:8: unexpected token '=' in a simultaneous statement list
libghdl: :52:7: '<=' is expected instead of 'on'
libghdl: :52:7: unexpected token 'on' in a primary
libghdl: :52:6: ';' expected at end of signal assignment
libghdl: :52:6: (found: 'on')
libghdl: :52:7: unexpected token 'on' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd] 0:00:00.237591

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:33: interfaces must be separated by ';' (found ',')
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:25: interfaces must be separated by ';' (found ',')
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "v_neg"
libghdl: :33:16: ';' expected at end of signal assignment
libghdl: :33:16: (found: ':=')
libghdl: :33:17: unexpected token ':=' in a concurrent statement list
libghdl: :34:11: '<=' is expected instead of "v_in"
libghdl: :34:15: ';' expected at end of signal assignment
libghdl: :34:15: (found: an identifier)
libghdl: :34:23: '<=' is expected instead of "plus_in"
libghdl: :34:30: ';' expected at end of signal assignment
libghdl: :34:30: (found: 'to')
libghdl: :34:31: unexpected token 'to' in a concurrent statement list
libghdl: :35:11: '<=' is expected instead of "v_out"
libghdl: :35:16: ';' expected at end of signal assignment
libghdl: :35:16: (found: an identifier)
libghdl: :35:24: '<=' is expected instead of "i_out"
libghdl: :35:29: ';' expected at end of signal assignment
libghdl: :35:29: (found: an identifier)
libghdl: :35:38: '<=' is expected instead of "output"
libghdl: :36:11: '<=' is expected instead of "v_amplified"
libghdl: :36:22: ';' expected at end of signal assignment
libghdl: :36:22: (found: ':')
libghdl: :36:23: unexpected token ':' in a concurrent statement list
libghdl: :38:0: unexpected token 'begin' in a concurrent statement list
libghdl: :40:30: if/use is an AMS-VHDL statement
libghdl: :41:16: '==' is not the vhdl equality, replaced by '='
libghdl: :41:16: '==' expected after expression
libghdl: :41:16: (found: '=')
libghdl: :41:16: unexpected token '=' in a primary
libghdl: :41:15: ';' is expected instead of '='
libghdl: :41:16: unexpected token '=' in a simultaneous statement list
libghdl: :43:16: '==' is not the vhdl equality, replaced by '='
libghdl: :43:16: '==' expected after expression
libghdl: :43:16: (found: '=')
libghdl: :43:16: unexpected token '=' in a primary
libghdl: :43:15: ';' is expected instead of '='
libghdl: :43:16: unexpected token '=' in a simultaneous statement list
libghdl: :45:16: '==' is not the vhdl equality, replaced by '='
libghdl: :45:16: '==' expected after expression
libghdl: :45:16: (found: '=')
libghdl: :45:16: unexpected token '=' in a primary
libghdl: :45:15: ';' is expected instead of '='
libghdl: :45:16: unexpected token '=' in a simultaneous statement list
libghdl: :48:8: '<=' is expected instead of 'on'
libghdl: :48:8: unexpected token 'on' in a primary
libghdl: :48:7: ';' expected at end of signal assignment
libghdl: :48:7: (found: 'on')
libghdl: :48:8: unexpected token 'on' in a concurrent statement list
libghdl: :50:8: '==' is not the vhdl equality, replaced by '='
libghdl: :50:8: '<=' is expected instead of '='
libghdl: :50:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd] 0:00:00.232736

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:23: ';' or ')' expected after interface
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:24: ';' or ')' expected after interface
libghdl: :52:4: object class keyword such as 'variable' is expected
libghdl: :53:4: 'begin' is expected instead of 'signal'
libghdl: :53:4: unexpected token 'signal' in a concurrent statement list
libghdl: :55:2: unexpected token 'begin' in a concurrent statement list
libghdl: :57:14: '==' is not the vhdl equality, replaced by '='
libghdl: :71:4: object class keyword such as 'variable' is expected
libghdl: :72:4: 'begin' is expected instead of 'signal'
libghdl: :72:4: unexpected token 'signal' in a concurrent statement list
libghdl: :73:4: unexpected token 'constant' in a concurrent statement list
libghdl: :75:2: unexpected token 'begin' in a concurrent statement list
libghdl: :77:14: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd] 0:00:00.246727

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd'
DOM: Error raised in libghdl.
libghdl: :37:4: object class keyword such as 'variable' is expected
libghdl: :43:19: '==' is not the vhdl equality, replaced by '='
libghdl: :43:19: '<=' is expected instead of '='
libghdl: :43:19: unexpected token '=' in a primary
libghdl: :53:4: object class keyword such as 'variable' is expected
libghdl: :60:19: '==' is not the vhdl equality, replaced by '='
libghdl: :60:19: '<=' is expected instead of '='
libghdl: :60:19: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd] 0:00:00.232900

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:20: ';' or ')' expected after interface
libghdl: :35:2: object class keyword such as 'variable' is expected
libghdl: :42:8: '==' is not the vhdl equality, replaced by '='
libghdl: :42:8: '<=' is expected instead of '='
libghdl: :42:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd] 0:00:00.236239

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd'
DOM: Error raised in libghdl.
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :35:2: 'begin' is expected instead of "subnature"
libghdl: :35:12: '<=' is expected instead of "accurate_electrical"
libghdl: :35:31: ';' expected at end of signal assignment
libghdl: :35:31: (found: 'is')
libghdl: :35:32: unexpected token 'is' in a concurrent statement list
libghdl: :40:11: '<=' is expected instead of "n1"
libghdl: :40:17: ';' expected at end of signal assignment
libghdl: :40:17: (found: ':')
libghdl: :40:18: unexpected token ':' in a concurrent statement list
libghdl: :44:11: '<=' is expected instead of "n1_n2_voltage"
libghdl: :44:24: ';' expected at end of signal assignment
libghdl: :44:24: (found: an identifier)
libghdl: :44:32: '<=' is expected instead of "n1_n2_current"
libghdl: :44:45: ';' expected at end of signal assignment
libghdl: :44:45: (found: an identifier)
libghdl: :44:54: '<=' is expected instead of "n1"
libghdl: :44:56: ';' expected at end of signal assignment
libghdl: :44:56: (found: 'to')
libghdl: :44:57: unexpected token 'to' in a concurrent statement list
libghdl: :48:11: '<=' is expected instead of "internal_voltage"
libghdl: :48:27: ';' expected at end of signal assignment
libghdl: :48:27: (found: ':')
libghdl: :48:28: unexpected token ':' in a concurrent statement list
libghdl: :49:11: '<=' is expected instead of "internal_current"
libghdl: :49:27: ';' expected at end of signal assignment
libghdl: :49:27: (found: ':')
libghdl: :49:28: unexpected token ':' in a concurrent statement list
libghdl: :53:11: '<=' is expected instead of "bus_a_end"
libghdl: :53:31: ';' expected at end of signal assignment
libghdl: :53:31: (found: ':')
libghdl: :53:32: unexpected token ':' in a concurrent statement list
libghdl: :54:11: '<=' is expected instead of "bus_currents"
libghdl: :54:23: ';' expected at end of signal assignment
libghdl: :54:23: (found: an identifier)
libghdl: :54:32: '<=' is expected instead of "bus_a_end"
libghdl: :54:41: ';' expected at end of signal assignment
libghdl: :54:41: (found: 'to')
libghdl: :54:42: unexpected token 'to' in a concurrent statement list
libghdl: :58:0: unexpected token 'begin' in a concurrent statement list
libghdl: :62:22: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd] 0:00:00.232894

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd'
libghdl processing time:  58.201 us
DOM translation time:    504.409 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_18a(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd':
      Entities:
        - Name: inline_18a
          File: inline_18a.vhd
          Position: 22:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_18a.vhd
          Position: 27:13
          Entity: inline_18a
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd] 0:00:00.237024

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd'
DOM: Error raised in libghdl.
libghdl: :23:17: ':' expected after interface identifier
libghdl: :23:17: (found: an identifier)
libghdl: :23:19: interfaces must be separated by ';' (found ',')
libghdl: :30:2: object class keyword such as 'variable' is expected
libghdl: :32:17: '==' is not the vhdl equality, replaced by '='
libghdl: :32:17: '<=' is expected instead of '='
libghdl: :32:17: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd] 0:00:00.238426

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd'
DOM: Error raised in libghdl.
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:19: interfaces must be separated by ';' (found ',')
libghdl: :28:18: ':' expected after interface identifier
libghdl: :28:18: (found: an identifier)
libghdl: :28:20: ';' or ')' expected after interface
libghdl: :42:2: object class keyword such as 'variable' is expected
libghdl: :43:2: 'begin' is expected instead of "quantity"
libghdl: :43:11: '<=' is expected instead of "vt"
libghdl: :43:13: ';' expected at end of signal assignment
libghdl: :43:13: (found: ':')
libghdl: :43:14: unexpected token ':' in a concurrent statement list
libghdl: :44:11: '<=' is expected instead of "temp"
libghdl: :44:15: ';' expected at end of signal assignment
libghdl: :44:15: (found: an identifier)
libghdl: :44:23: '<=' is expected instead of "power"
libghdl: :44:28: ';' expected at end of signal assignment
libghdl: :44:28: (found: an identifier)
libghdl: :44:37: '<=' is expected instead of "j"
libghdl: :46:0: unexpected token 'begin' in a concurrent statement list
libghdl: :48:5: '==' is not the vhdl equality, replaced by '='
libghdl: :50:5: '==' is not the vhdl equality, replaced by '='
libghdl: :50:5: '<=' is expected instead of '='
libghdl: :50:5: unexpected token '=' in a primary
libghdl: :52:8: '==' is not the vhdl equality, replaced by '='
libghdl: :52:8: '<=' is expected instead of '='
libghdl: :52:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd] 0:00:00.244939

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd'
DOM: Error raised in libghdl.
libghdl: :37:2: object class keyword such as 'variable' is expected
libghdl: :38:2: 'begin' is expected instead of "quantity"
libghdl: :38:11: '<=' is expected instead of "v"
libghdl: :38:12: ';' expected at end of signal assignment
libghdl: :38:12: (found: an identifier)
libghdl: :38:20: '<=' is expected instead of "i"
libghdl: :38:21: ';' expected at end of signal assignment
libghdl: :38:21: (found: an identifier)
libghdl: :38:30: '<=' is expected instead of "p"
libghdl: :38:31: ';' expected at end of signal assignment
libghdl: :38:31: (found: 'to')
libghdl: :38:32: unexpected token 'to' in a concurrent statement list
libghdl: :42:11: '<=' is expected instead of "node1"
libghdl: :42:23: ';' expected at end of signal assignment
libghdl: :42:23: (found: ':')
libghdl: :42:24: unexpected token ':' in a concurrent statement list
libghdl: :43:11: '<=' is expected instead of "d"
libghdl: :43:12: ';' expected at end of signal assignment
libghdl: :43:12: (found: an identifier)
libghdl: :43:20: '<=' is expected instead of "f"
libghdl: :43:21: ';' expected at end of signal assignment
libghdl: :43:21: (found: an identifier)
libghdl: :43:30: '<=' is expected instead of "node1"
libghdl: :43:35: ';' expected at end of signal assignment
libghdl: :43:35: (found: 'to')
libghdl: :43:36: unexpected token 'to' in a concurrent statement list
libghdl: :47:0: unexpected token 'begin' in a concurrent statement list
libghdl: :51:4: '==' is not the vhdl equality, replaced by '='
libghdl: :55:4: '==' is not the vhdl equality, replaced by '='
libghdl: :55:4: '<=' is expected instead of '='
libghdl: :55:4: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd] 0:00:00.230219

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd'
DOM: Error raised in libghdl.
libghdl: :29:4: object class keyword such as 'variable' is expected
libghdl: :30:4: 'begin' is expected instead of "terminal"
libghdl: :30:13: '<=' is expected instead of "vout"
libghdl: :30:17: ';' expected at end of signal assignment
libghdl: :30:17: (found: ':')
libghdl: :30:18: unexpected token ':' in a concurrent statement list
libghdl: :31:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd] 0:00:00.246344

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd'
DOM: Error raised in libghdl.
libghdl: :33:2: object class keyword such as 'variable' is expected
libghdl: :34:2: 'begin' is expected instead of "quantity"
libghdl: :34:11: '<=' is expected instead of "ambient"
libghdl: :34:18: ';' expected at end of signal assignment
libghdl: :34:18: (found: ':')
libghdl: :34:19: unexpected token ':' in a concurrent statement list
libghdl: :38:0: unexpected token 'begin' in a concurrent statement list
libghdl: :40:10: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd] 0:00:00.246796

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd'
DOM: Error raised in libghdl.
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :32:2: 'begin' is expected instead of "terminal"
libghdl: :32:11: '<=' is expected instead of "b_bus"
libghdl: :32:16: ';' expected at end of signal assignment
libghdl: :32:16: (found: ':')
libghdl: :32:17: unexpected token ':' in a concurrent statement list
libghdl: :36:11: '<=' is expected instead of "a_to_b_drops"
libghdl: :36:23: ';' expected at end of signal assignment
libghdl: :36:23: (found: an identifier)
libghdl: :36:31: '<=' is expected instead of "a_to_b_currents"
libghdl: :36:46: ';' expected at end of signal assignment
libghdl: :36:46: (found: an identifier)
libghdl: :36:55: '<=' is expected instead of "a_bus"
libghdl: :36:60: ';' expected at end of signal assignment
libghdl: :36:60: (found: 'to')
libghdl: :36:61: unexpected token 'to' in a concurrent statement list
libghdl: :40:9: '<=' is expected instead of "electrical_bus"
libghdl: :40:23: ';' expected at end of signal assignment
libghdl: :40:23: (found: 'is')
libghdl: :40:24: unexpected token 'is' in a concurrent statement list
libghdl: :44:7: missing ";" at end of architecture
libghdl: :46:2: missing entity, architecture, package or configuration
libghdl: :50:2: missing entity, architecture, package or configuration
libghdl: :54:2: missing entity, architecture, package or configuration
libghdl: :56:2: missing entity, architecture, package or configuration
libghdl: :61:0: missing entity, architecture, package or configuration
libghdl: :69:4: missing entity, architecture, package or configuration
libghdl: :74:2: missing entity, architecture, package or configuration
libghdl: :78:2: missing entity, architecture, package or configuration
libghdl: :84:4: missing entity, architecture, package or configuration
libghdl: :90:2: missing entity, architecture, package or configuration
libghdl: :94:0: missing entity, architecture, package or configuration

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd] 0:00:00.261022

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd'
DOM: Error raised in libghdl.
libghdl: :33:2: object class keyword such as 'variable' is expected
libghdl: :35:2: 'begin' is expected instead of "limit"
libghdl: :35:8: '<=' is expected instead of "d"
libghdl: :35:9: ';' expected at end of signal assignment
libghdl: :35:9: (found: ':')
libghdl: :35:10: unexpected token ':' in a concurrent statement list
libghdl: :39:11: '<=' is expected instead of "drive_shaft_av"
libghdl: :39:44: ';' expected at end of signal assignment
libghdl: :39:44: (found: ':')
libghdl: :39:45: unexpected token ':' in a concurrent statement list
libghdl: :43:8: '<=' is expected instead of "drive_shaft_av"
libghdl: :43:41: ';' expected at end of signal assignment
libghdl: :43:41: (found: ':')
libghdl: :43:42: unexpected token ':' in a concurrent statement list
libghdl: :47:8: '<=' is expected instead of 'all'
libghdl: :47:8: unexpected token 'all' in a primary
libghdl: :47:7: ';' expected at end of signal assignment
libghdl: :47:7: (found: 'all')
libghdl: :47:8: unexpected token 'all' in a concurrent statement list
libghdl: :51:11: '<=' is expected instead of "input"
libghdl: :51:48: ';' expected at end of signal assignment
libghdl: :51:48: (found: ':')
libghdl: :51:49: unexpected token ':' in a concurrent statement list
libghdl: :53:8: '<=' is expected instead of "input"
libghdl: :53:25: ';' expected at end of signal assignment
libghdl: :53:25: (found: ':')
libghdl: :53:26: unexpected token ':' in a concurrent statement list
libghdl: :54:8: '<=' is expected instead of 'others'
libghdl: :54:8: unexpected token 'others' in a primary
libghdl: :54:7: ';' expected at end of signal assignment
libghdl: :54:7: (found: 'others')
libghdl: :54:8: unexpected token 'others' in a concurrent statement list
libghdl: :58:11: '<=' is expected instead of "bus1"
libghdl: :58:15: ';' expected at end of signal assignment
libghdl: :58:15: (found: ':')
libghdl: :58:16: unexpected token ':' in a concurrent statement list
libghdl: :59:11: '<=' is expected instead of "bus2"
libghdl: :59:15: ';' expected at end of signal assignment
libghdl: :59:15: (found: ':')
libghdl: :59:16: unexpected token ':' in a concurrent statement list
libghdl: :60:11: '<=' is expected instead of "v_bus"
libghdl: :60:16: ';' expected at end of signal assignment
libghdl: :60:16: (found: an identifier)
libghdl: :60:24: '<=' is expected instead of "bus1"
libghdl: :60:28: ';' expected at end of signal assignment
libghdl: :60:28: (found: 'to')
libghdl: :60:29: unexpected token 'to' in a concurrent statement list
libghdl: :61:8: '<=' is expected instead of "v_bus"
libghdl: :61:13: ';' expected at end of signal assignment
libghdl: :61:13: (found: ':')
libghdl: :61:14: unexpected token ':' in a concurrent statement list
libghdl: :65:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd] 0:00:00.239296

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd'
DOM: Error raised in libghdl.
libghdl: :29:4: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd] 0:00:00.251764

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:20: interfaces must be separated by ';' (found ',')
libghdl: :26:18: ':' expected after interface identifier
libghdl: :26:18: (found: an identifier)
libghdl: :26:23: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "v"
libghdl: :33:12: ';' expected at end of signal assignment
libghdl: :33:12: (found: an identifier)
libghdl: :33:20: '<=' is expected instead of "i"
libghdl: :33:21: ';' expected at end of signal assignment
libghdl: :33:21: (found: an identifier)
libghdl: :33:30: '<=' is expected instead of "n1"
libghdl: :33:32: ';' expected at end of signal assignment
libghdl: :33:32: (found: 'to')
libghdl: :33:33: unexpected token 'to' in a concurrent statement list
libghdl: :34:0: unexpected token 'begin' in a concurrent statement list
libghdl: :35:13: '==' is not the vhdl equality, replaced by '='
libghdl: :36:4: '==' is not the vhdl equality, replaced by '='
libghdl: :36:4: '<=' is expected instead of '='
libghdl: :36:4: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd] 0:00:00.240381

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd'
DOM: Error raised in libghdl.
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :32:2: 'begin' is expected instead of "quantity"
libghdl: :32:11: '<=' is expected instead of "v_rc_ext"
libghdl: :32:19: ';' expected at end of signal assignment
libghdl: :32:19: (found: an identifier)
libghdl: :32:27: '<=' is expected instead of "rc_ext"
libghdl: :33:2: unexpected token 'constant' in a concurrent statement list
libghdl: :35:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:12: a block statement must have a label
libghdl: :63:12: end label for an unlabeled declaration or statement

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd] 0:00:00.233291

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:22: ';' or ')' expected after interface
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:23: ';' or ')' expected after interface
libghdl: :33:7: '==' is not the vhdl equality, replaced by '='
libghdl: :33:7: '<=' is expected instead of '='
libghdl: :33:7: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd] 0:00:00.226700

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:38: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "velocity"
libghdl: :33:19: ';' expected at end of signal assignment
libghdl: :33:19: (found: ':')
libghdl: :33:20: unexpected token ':' in a concurrent statement list
libghdl: :34:0: unexpected token 'begin' in a concurrent statement list
libghdl: :35:11: '==' is not the vhdl equality, replaced by '='
libghdl: :36:22: '==' is not the vhdl equality, replaced by '='
libghdl: :36:22: '<=' is expected instead of '='
libghdl: :36:22: unexpected token '=' in a primary
libghdl: :36:88: ';' expected at end of signal assignment
libghdl: :36:88: (found: an identifier)
libghdl: :37:14: '<=' is expected instead of "velocity"

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd] 0:00:00.245719

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:23: interfaces must be separated by ';' (found ',')
libghdl: :29:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd] 0:00:00.237194

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd'
libghdl processing time:  109.402 us
DOM translation time:    1104.421 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - reg(gate_level)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd':
      Entities:
        - Name: reg
          File: reg-1.vhd
          Position: 22:7
          Generics:
            - t_setup, t_hold, t_pd : in delay_length
            - width : in positive
          Ports:
            - clock : in std_logic
            - reset_n : in std_logic := H
            - data_in : in std_logic_vector(0 to width - 1)
            - data_out : out std_logic_vector(0 to width - 1)
          Declared:
          Statements:
          Architecures:
          - gate_level
      Architectures:
        - Name: gate_level
          File: reg-1.vhd
          Position: 35:13
          Entity: reg
          Declared:
          Hierarchy:
            - store: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd] 0:00:00.230382

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:20: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd] 0:00:00.234216

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd'
DOM: Error raised in libghdl.
libghdl: :25:2: object class keyword such as 'variable' is expected
libghdl: :28:2: 'end' is expected instead of "subnature"
libghdl: :28:2: misspelling, "automotive_valve_defs" expected
libghdl: :28:11: missing ";" at end of package declaration
libghdl: :33:2: missing entity, architecture, package or configuration
libghdl: :35:11: missing entity, architecture, package or configuration
libghdl: :36:2: missing entity, architecture, package or configuration
libghdl: :38:0: missing entity, architecture, package or configuration

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd] 0:00:00.233668

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd'
DOM: Error raised in libghdl.
libghdl: :29:1: object class keyword such as 'variable' is expected
libghdl: :30:4: 'begin' is expected instead of 'signal'
libghdl: :30:4: unexpected token 'signal' in a concurrent statement list
libghdl: :31:1: unexpected token 'signal' in a concurrent statement list
libghdl: :33:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd] 0:00:00.236990

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd'
[NOT IMPLEMENTED] Configuration specification in structural
libghdl processing time:  225.704 us
DOM translation time:    4252.178 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - control_section(structural)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd':
      Entities:
        - Name: control_section
          File: control_section.vhd
          Position: 24:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - structural
      Architectures:
        - Name: structural
          File: control_section.vhd
          Position: 30:13
          Entity: control_section
          Declared:
            - Component: reg
              Generics:
                - width : in positive
              Ports:
                - clk : in std_logic
                - d : in std_logic_vector(0 to width - 1)
                - q : out std_logic_vector(0 to width - 1)
            - signal clock_phase1, zero_result, neg_result, overflow_result, zero_flag, neg_flag, overflow_flag : std_logic
          Hierarchy:
            - flag_reg: component reg
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd] 0:00:00.235643

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd'
libghdl processing time:  127.702 us
DOM translation time:    770.014 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_05(test)
        - nand2()
      Packages:
      Configurations:
        - inline_05_test
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd':
      Entities:
        - Name: inline_05
          File: inline_05.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
        - Name: nand2
          File: inline_05.vhd
          Position: 51:7
          Generics:
          Ports:
            - a, b : in bit := 1
            - y : out bit
          Declared:
          Statements:
          Architecures:
      Architectures:
        - Name: test
          File: inline_05.vhd
          Position: 24:13
          Entity: inline_05
          Declared:
            - Component: nand3
              Generics:
              Ports:
                - a, b, c : in bit := 1
                - y : out bit
            - signal s1, s2, s3 : bit
          Hierarchy:
            - gate1: component nand3
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
        - Name: inline_05_test
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd] 0:00:00.233683

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd'
DOM: Error raised in libghdl.
libghdl: :26:18: ':' expected after interface identifier
libghdl: :26:18: (found: an identifier)
libghdl: :26:28: ';' or ')' expected after interface

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd] 0:00:00.226668

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd'
DOM: Error raised in libghdl.
libghdl: :29:20: ':' expected after interface identifier
libghdl: :29:20: (found: an identifier)
libghdl: :29:27: interfaces must be separated by ';' (found ',')
libghdl: :32:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd] 0:00:00.235307

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd'
DOM: Error raised in libghdl.
libghdl: :38:2: object class keyword such as 'variable' is expected
libghdl: :39:2: 'begin' is expected instead of "terminal"
libghdl: :39:11: '<=' is expected instead of "brake_pedal"
libghdl: :39:22: ';' expected at end of signal assignment
libghdl: :39:22: (found: ':')
libghdl: :39:23: unexpected token ':' in a concurrent statement list
libghdl: :42:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd] 0:00:00.239776

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd'
DOM: Error raised in libghdl.
libghdl: :33:2: object class keyword such as 'variable' is expected
libghdl: :34:2: 'begin' is expected instead of "terminal"
libghdl: :34:11: '<=' is expected instead of "right_decoded"
libghdl: :34:40: ';' expected at end of signal assignment
libghdl: :34:40: (found: ':')
libghdl: :34:41: unexpected token ':' in a concurrent statement list
libghdl: :37:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd] 0:00:00.241773

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd'
libghdl processing time:  152.003 us
DOM translation time:    1275.123 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - single_board_computer(structural)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd':
      Entities:
        - Name: single_board_computer
          File: single_board_computer.vhd
          Position: 21:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - structural
      Architectures:
        - Name: structural
          File: single_board_computer.vhd
          Position: 26:13
          Entity: single_board_computer
          Declared:
            - subtype word is ?????
            - signal sys_clk : bit
            - signal cpu_a_d, latched_addr : word
            - Component: processor
              Generics:
              Ports:
                - clk : in bit
                - a_d : inout word
                - other_port : in bit := 0
            - Component: memory
              Generics:
              Ports:
                - addr : in bit_vector(25 downto 0)
                - other_port : in bit := 0
            - Component: serial_interface
              Generics:
              Ports:
                - clk : in bit
                - address : in bit_vector(3 downto 0)
                - other_port : in bit := 0
          Hierarchy:
            - cpu: component processor
            - main_memory: component memory
            - serial_interface_a: component serial_interface
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd] 0:00:00.259956

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:20: interfaces must be separated by ';' (found ',')
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:26: ';' or ')' expected after interface

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd] 0:00:00.226299

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd'
libghdl processing time:  73.601 us
DOM translation time:    135.803 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - full
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: full
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd] 0:00:00.275653

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:23: interfaces must be separated by ';' (found ',')
libghdl: :31:20: ':' expected after interface identifier
libghdl: :31:20: (found: an identifier)
libghdl: :31:27: interfaces must be separated by ';' (found ',')
libghdl: :35:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd] 0:00:00.253370

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 46
[NOT IMPLEMENTED] Configuration specification in detailed_timing
libghdl processing time:  252.305 us
DOM translation time:    10483.692 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - nor_gate(primitive)
        - interlock_control(detailed_timing)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd':
      Entities:
        - Name: nor_gate
          File: interlock_control.vhd
          Position: 22:7
          Generics:
            - width : in positive
            - Tpd01, Tpd10 : in delay_length
          Ports:
            - input : in std_logic_vector(0 to width - 1)
            - output : out std_logic
          Declared:
          Statements:
          Architecures:
          - primitive
        - Name: interlock_control
          File: interlock_control.vhd
          Position: 65:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - detailed_timing
      Architectures:
        - Name: primitive
          File: interlock_control.vhd
          Position: 30:13
          Entity: nor_gate
          Declared:
            - function max return delay_length
          Hierarchy:
            - reducer: process(...)
          Statements:
            ...
        - Name: detailed_timing
          File: interlock_control.vhd
          Position: 71:13
          Entity: interlock_control
          Declared:
            - Component: nor_gate
              Generics:
                - input_width : in positive
              Ports:
                - input : in std_logic_vector(0 to input_width - 1)
                - output : out std_logic
            - signal reg_access_hazard, load_hazard, stall_ex_n : std_logic
          Hierarchy:
            - ex_interlock_gate: component nor_gate
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd] 0:00:00.330456

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd'
libghdl processing time:  90.802 us
DOM translation time:    80.701 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - misc_logic_reconfigured
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: misc_logic_reconfigured
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd] 0:00:00.319210

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd'
libghdl processing time:  70.302 us
DOM translation time:    55.101 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - notch_filter_down_to_device_level
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: notch_filter_down_to_device_level
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd] 0:00:00.233877

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd'
libghdl processing time:  67.901 us
DOM translation time:    165.203 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - opamp_mosfets
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: opamp_mosfets
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd] 0:00:00.222192

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:22: interfaces must be separated by ';' (found ',')
libghdl: :44:18: ':' expected after interface identifier
libghdl: :44:18: (found: an identifier)
libghdl: :44:25: interfaces must be separated by ';' (found ',')
libghdl: :54:20: ':' expected after interface identifier
libghdl: :54:20: (found: an identifier)
libghdl: :54:24: interfaces must be separated by ';' (found ',')
libghdl: :57:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd] 0:00:00.231277

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd'
libghdl processing time:  93.002 us
DOM translation time:    80.402 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - computer_structure
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: computer_structure
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd] 0:00:00.235824

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd'
libghdl processing time:  146.403 us
DOM translation time:    976.118 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - computer_system(structure)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd':
      Entities:
        - Name: computer_system
          File: computer_system.vhd
          Position: 22:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - structure
      Architectures:
        - Name: structure
          File: computer_system.vhd
          Position: 31:13
          Entity: computer_system
          Declared:
            - Component: decoder_2_to_4
              Generics:
                - prop_delay : in delay_length
              Ports:
                - in0, in1 : in bit
                - out0, out1, out2, out3 : out bit
            - signal addr : bit_vector(5 downto 4)
            - signal interface_a_select, interface_b_select, interface_c_select, interface_d_select : bit
          Hierarchy:
            - interface_decoder: component decoder_2_to_4
            - None: all_possible_values(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd] 0:00:00.242913

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd'
libghdl processing time:  109.002 us
DOM translation time:    64.502 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - sensor_interface_with_timing
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: sensor_interface_with_timing
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd] 0:00:00.307200

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd'
DOM: Error raised in libghdl.
libghdl: :37:20: ':' expected after interface identifier
libghdl: :37:20: (found: an identifier)
libghdl: :37:30: ';' or ')' expected after interface
libghdl: :47:2: object class keyword such as 'variable' is expected
libghdl: :48:2: 'begin' is expected instead of 'signal'
libghdl: :48:2: unexpected token 'signal' in a concurrent statement list
libghdl: :49:2: unexpected token 'signal' in a concurrent statement list
libghdl: :52:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd] 0:00:00.236690

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd'
libghdl processing time:  78.902 us
DOM translation time:    56.101 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - controller_with_timing
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: controller_with_timing
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd] 0:00:00.237716

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd'
libghdl processing time:  66.001 us
DOM translation time:    56.901 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - inline_02a
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: inline_02a
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd] 0:00:00.234961

Setup

Call

[gw1] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd'
DOM: Unknown name kind 'Aggregate'

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd] 0:00:00.259008

Setup

Call

[gw0] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd'
[NOT IMPLEMENTED] Configuration specification in gate_level
DOM: Unknown name kind 'Aggregate'

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd] 0:00:00.234891

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd'
libghdl processing time:  59.901 us
DOM translation time:    405.008 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - IO_section()
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd':
      Entities:
        - Name: IO_section
          File: inline_03.vhd
          Position: 22:7
          Generics:
          Ports:
            - data_ack : inout std_logic
            - other_port : in std_ulogic := U
          Declared:
          Statements:
          Architecures:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd] 0:00:00.242090

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd'
[NOT IMPLEMENTED] Configuration specification in ideal
libghdl processing time:  151.802 us
DOM translation time:    1298.724 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - nand3(behavioral)
        - logic_block(ideal)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd':
      Entities:
        - Name: nand3
          File: logic_block.vhd
          Position: 22:7
          Generics:
          Ports:
            - a, b, c : in bit
            - y : out bit
          Declared:
          Statements:
          Architecures:
          - behavioral
        - Name: logic_block
          File: logic_block.vhd
          Position: 35:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - ideal
      Architectures:
        - Name: behavioral
          File: logic_block.vhd
          Position: 28:13
          Entity: nand3
          Declared:
          Hierarchy:
          Statements:
            ...
        - Name: ideal
          File: logic_block.vhd
          Position: 43:13
          Entity: logic_block
          Declared:
            - Component: nand2
              Generics:
              Ports:
                - in1, in2 : in bit
                - result : out bit
            - signal s1, s2, s3 : bit := 0
          Hierarchy:
            - gate1: component nand2
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd] 0:00:00.241063

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd'
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  124.002 us
DOM translation time:    556.311 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - inline_02
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: inline_02
          File: inline_02.vhd
          Position: 20:8
          Declared:
          - type std_ulogic is (........)
          - type std_ulogic_vector is array(........) of .....
          - subtype std_logic is ?????
          - type std_logic_vector is array(........) of .....
          - subtype X01 is ?????
          - subtype X01Z is ?????
          - subtype UX01 is ?????
          - subtype UX01Z is ?????
      PackageBodies:
        - Name: inline_02
          Declared:
          - function resolved return std_ulogic
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd] 0:00:00.231720

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd'
libghdl processing time:  132.003 us
DOM translation time:    600.511 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - XYZ3000_cpu(full_function)
        - memory_array(behavioral)
      Packages:
      Configurations:
        - intermediate
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd':
      Entities:
        - Name: XYZ3000_cpu
          File: intermediate.vhd
          Position: 22:7
          Generics:
          Ports:
            - clock : in bit
            - addr_data : inout bit_vector(31 downto 0)
            - other_port : in bit := 0
          Declared:
          Statements:
          Architecures:
          - full_function
        - Name: memory_array
          File: intermediate.vhd
          Position: 35:7
          Generics:
          Ports:
            - addr : in bit_vector(25 downto 0)
            - other_port : in bit := 0
          Declared:
          Statements:
          Architecures:
          - behavioral
      Architectures:
        - Name: full_function
          File: intermediate.vhd
          Position: 28:13
          Entity: XYZ3000_cpu
          Declared:
          Hierarchy:
          Statements:
        - Name: behavioral
          File: intermediate.vhd
          Position: 40:13
          Entity: memory_array
          Declared:
          Hierarchy:
          Statements:
      Packages:
      PackageBodies:
      Configurations:
        - Name: intermediate
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd] 0:00:00.235717

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd'
libghdl processing time:  181.703 us
DOM translation time:    1761.632 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - ROM(behavioral)
        - SIMM(behavioral)
        - memory_subsystem(detailed)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd':
      Entities:
        - Name: ROM
          File: memory_system.vhd
          Position: 22:7
          Generics:
          Ports:
            - a : in MVL4_ulogic_vector(15 downto 0)
            - d : inout MVL4_logic_vector(7 downto 0)
            - rd : in MVL4_ulogic
          Declared:
          Statements:
          Architecures:
          - behavioral
        - Name: SIMM
          File: memory_system.vhd
          Position: 38:7
          Generics:
          Ports:
            - a : in MVL4_ulogic_vector(9 downto 0)
            - d : inout MVL4_logic_vector(31 downto 0)
            - ras, cas, we, cs : in MVL4_ulogic
          Declared:
          Statements:
          Architecures:
          - behavioral
        - Name: memory_subsystem
          File: memory_system.vhd
          Position: 56:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - detailed
      Architectures:
        - Name: behavioral
          File: memory_system.vhd
          Position: 29:13
          Entity: ROM
          Declared:
          Hierarchy:
          Statements:
        - Name: behavioral
          File: memory_system.vhd
          Position: 45:13
          Entity: SIMM
          Declared:
          Hierarchy:
          Statements:
        - Name: detailed
          File: memory_system.vhd
          Position: 61:13
          Entity: memory_subsystem
          Declared:
            - signal internal_data : MVL4_logic_vector(31 downto 0)
            - signal internal_addr : MVL4_ulogic_vector(31 downto 0)
            - signal main_mem_addr : MVL4_ulogic_vector(9 downto 0)
            - signal ROM_select : MVL4_ulogic
          Hierarchy:
            - boot_rom: entity work.ROM
            - main_mem: entity work.SIMM
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd] 0:00:00.225026

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd'
libghdl processing time:  68.701 us
DOM translation time:    79.802 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - interlock_control_with_estimates
        - interlock_control_with_actual
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: interlock_control_with_estimates
        - Name: interlock_control_with_actual
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd] 0:00:00.225577

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd'
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  141.503 us
DOM translation time:    829.115 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - MVL4
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: MVL4
          File: MVL4.vhd
          Position: 20:8
          Declared:
          - type MVL4_ulogic is (........)
          - type MVL4_ulogic_vector is array(........) of .....
          - subtype MVL4_logic is ?????
          - type MVL4_logic_vector is array(........) of .....
      PackageBodies:
        - Name: MVL4
          Declared:
          - type ???? is array(........) of .....
          - constant resolution_table : table := ((X, X, X, X), (X, 0, X, 0), (X, X, 1, 1), (X, 0, 1, Z))
          - function resolve_MVL4 return MVL4_ulogic
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd] 0:00:00.234659

Setup

Call

[gw1] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd'
DOM: Unknown statement of kind 'While_Loop_Statement' in process 'synchronized_module' at /home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd:44:4.

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd] 0:00:00.230102

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd'
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  177.503 us
DOM translation time:    1621.030 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - resolved
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: resolved
          File: resolved.vhd
          Position: 20:8
          Declared:
          - type std_ulogic is (........)
          - type std_ulogic_vector is array(........) of .....
      PackageBodies:
        - Name: resolved
          Declared:
          - type ???? is array(........) of .....
          - constant resolution_table : stdlogic_table := ((U, U, U, U, U, U, U, U, U), (U, X, X, X, X, X, X, X, X), (U, X, 0, X, 0, 0, 0, 0, X), (U, X, X, 1, 1, 1, 1, 1, X), (U, X, 0, 1, Z, W, L, H, X), (U, X, 0, 1, W, W, W, W, X), (U, X, 0, 1, L, W, L, W, X), (U, X, 0, 1, H, W, W, H, X), (U, X, X, X, X, X, X, X, X))
          - function resolved return std_ulogic
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd] 0:00:00.241159

Setup

Call

[gw0] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd'],)
kwargs = {'stderr': -2}, retcode = 1
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd']' returned non-zero exit status 1.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd'

raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : vhdl-nodes.adb:3748

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd] 0:00:00.236030

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd'
libghdl processing time:  123.103 us
DOM translation time:    1443.326 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - bus_module(behavioral)
        - bus_based_system(top_level)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd':
      Entities:
        - Name: bus_module
          File: bus_based_system.vhd
          Position: 22:7
          Generics:
          Ports:
            - synch : inout std_ulogic
            - other_port : in std_ulogic := U
          Declared:
          Statements:
          Architecures:
          - behavioral
        - Name: bus_based_system
          File: bus_based_system.vhd
          Position: 37:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - top_level
      Architectures:
        - Name: top_level
          File: bus_based_system.vhd
          Position: 43:13
          Entity: bus_based_system
          Declared:
            - signal synch_control : std_logic
          Hierarchy:
            - bus_module_1: entity work.bus_module
            - bus_module_2: entity work.bus_module
          Statements:
            ...
            ...
            ...
        - Name: behavioral
          File: bus_based_system.vhd
          Position: 70:13
          Entity: bus_module
          Declared:
          Hierarchy:
            - behavior: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd] 0:00:00.232290

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd'
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
libghdl processing time:  172.103 us
DOM translation time:    596.911 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - synchronize
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: synchronize
          File: synchronize.vhd
          Position: 22:8
          Declared:
      PackageBodies:
        - Name: synchronize
          Declared:
          - procedure init_synchronize
          - procedure begin_synchronize
          - procedure end_synchronize
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd] 0:00:00.245103

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd'
libghdl processing time:  151.902 us
DOM translation time:    2955.154 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - misc_logic(gate_level)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd':
      Entities:
        - Name: misc_logic
          File: misc_logic.vhd
          Position: 22:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - gate_level
      Architectures:
        - Name: gate_level
          File: misc_logic.vhd
          Position: 31:13
          Entity: misc_logic
          Declared:
            - signal src1, src1_enable : MVL4_ulogic
            - signal src2, src2_enable : MVL4_ulogic
            - signal selected_val : MVL4_logic
          Hierarchy:
            - src1_buffer: entity work.tri_state_buffer
            - src2_buffer: entity work.tri_state_buffer
            - stimulus: process(...)
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd] 0:00:00.246536

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  159.603 us
DOM translation time:    1080.520 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - words
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: words
          File: words.vhd
          Position: 20:8
          Declared:
          - type X01Z is (........)
          - type ???? is array(........) of .....
          - type uword_vector is array(........) of .....
          - subtype word is ?????
          - type ???? is array(........) of .....
      PackageBodies:
        - Name: words
          Declared:
          - type ???? is array(........) of .....
          - constant resolution_table : table := ((X, X, X, X), (X, 0, X, 0), (X, X, 1, 1), (X, 0, 1, Z))
          - function resolve_word return uword
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd] 0:00:00.244926

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 31
libghdl processing time:  97.202 us
DOM translation time:    504.509 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tri_state_buffer(behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd':
      Entities:
        - Name: tri_state_buffer
          File: tri_state_buffer.vhd
          Position: 22:7
          Generics:
          Ports:
            - a, enable : in MVL4_ulogic
            - y : out MVL4_ulogic
          Declared:
          Statements:
          Architecures:
          - behavioral
      Architectures:
        - Name: behavioral
          File: tri_state_buffer.vhd
          Position: 28:13
          Entity: tri_state_buffer
          Declared:
          Hierarchy:
          Statements:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd] 0:00:00.252452

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:23: ';' or ')' expected after interface
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:20: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "v_amplified"
libghdl: :33:22: ';' expected at end of signal assignment
libghdl: :33:22: (found: ':')
libghdl: :33:23: unexpected token ':' in a concurrent statement list
libghdl: :35:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:14: '==' is not the vhdl equality, replaced by '='
libghdl: :57:2: object class keyword such as 'variable' is expected
libghdl: :58:2: 'begin' is expected instead of "quantity"
libghdl: :58:11: '<=' is expected instead of "v_ref"
libghdl: :58:16: ';' expected at end of signal assignment
libghdl: :58:16: (found: an identifier)
libghdl: :58:24: '<=' is expected instead of "i_ref"
libghdl: :58:29: ';' expected at end of signal assignment
libghdl: :58:29: (found: an identifier)
libghdl: :58:38: '<=' is expected instead of "ref"
libghdl: :59:2: unexpected token 'signal' in a concurrent statement list
libghdl: :61:0: unexpected token 'begin' in a concurrent statement list
libghdl: :78:8: '==' is not the vhdl equality, replaced by '='
libghdl: :78:8: '<=' is expected instead of '='
libghdl: :78:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd] 0:00:00.238081

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd'
DOM: Error raised in libghdl.
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :32:2: 'begin' is expected instead of "terminal"
libghdl: :32:11: '<=' is expected instead of "shaft1"
libghdl: :32:33: ';' expected at end of signal assignment
libghdl: :32:33: (found: ':')
libghdl: :32:34: unexpected token ':' in a concurrent statement list
libghdl: :33:2: unexpected token 'signal' in a concurrent statement list
libghdl: :35:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd] 0:00:00.260414

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd'
libghdl processing time:  166.503 us
DOM translation time:    1401.826 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - cpu(behavioral)
        - memory(behavioral)
        - ROM(behavioral)
        - computer_system(top_level)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd':
      Entities:
        - Name: cpu
          File: computer_system.vhd
          Position: 22:7
          Generics:
          Ports:
            - address : out uword
            - data : inout uword
            - other_port : in X01Z := Z
          Declared:
          Statements:
          Architecures:
          - behavioral
        - Name: memory
          File: computer_system.vhd
          Position: 43:7
          Generics:
          Ports:
            - address : in uword
            - data : inout uword
            - other_port : in X01Z := Z
          Declared:
          Statements:
          Architecures:
          - behavioral
        - Name: ROM
          File: computer_system.vhd
          Position: 67:7
          Generics:
          Ports:
            - a : in uword
            - d : out ubyte
            - other_port : in X01Z := Z
          Declared:
          Statements:
          Architecures:
          - behavioral
        - Name: computer_system
          File: computer_system.vhd
          Position: 77:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - top_level
      Architectures:
        - Name: behavioral
          File: computer_system.vhd
          Position: 32:13
          Entity: cpu
          Declared:
          Hierarchy:
          Statements:
        - Name: behavioral
          File: computer_system.vhd
          Position: 53:13
          Entity: memory
          Declared:
          Hierarchy:
          Statements:
        - Name: behavioral
          File: computer_system.vhd
          Position: 72:13
          Entity: ROM
          Declared:
          Hierarchy:
          Statements:
        - Name: top_level
          File: computer_system.vhd
          Position: 84:13
          Entity: computer_system
          Declared:
            - use work.words.all
            - signal address : uword
            - signal data : word
          Hierarchy:
            - the_cpu: entity work.cpu
            - the_memory: entity work.memory
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd] 0:00:00.231103

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd'
DOM: Error raised in libghdl.
libghdl: :34:5: object class keyword such as 'variable' is expected
libghdl: :35:1: 'begin' is expected instead of "quantity"
libghdl: :35:10: '<=' is expected instead of "gain"
libghdl: :35:14: ';' expected at end of signal assignment
libghdl: :35:14: (found: ':')
libghdl: :35:15: unexpected token ':' in a concurrent statement list
libghdl: :36:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd] 0:00:00.244785

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  179.003 us
DOM translation time:    1361.425 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_01(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd':
      Entities:
        - Name: inline_01
          File: inline_01.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_01.vhd
          Position: 28:13
          Entity: inline_01
          Declared:
            - type MVL4_ulogic is (........)
            - type small_int is range 1 to 4
            - type small_array is array(........) of .....
            - type ???? is array(........) of .....
            - constant resolution_table : table := ((X, X, X, X), (X, 0, X, 0), (X, X, 1, 1), (X, 0, 1, Z))
            - function resolve_MVL4 return MVL4_ulogic
            - subtype MVL4_logic is ?????
            - signal s : MVL4_logic
          Hierarchy:
          Statements:
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd] 0:00:00.252955

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd'
libghdl processing time:  255.305 us
DOM translation time:    2279.341 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - test_bench(example)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd':
      Entities:
        - Name: test_bench
          File: test_bench-1.vhd
          Position: 24:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - example
      Architectures:
        - Name: example
          File: test_bench-1.vhd
          Position: 27:13
          Entity: test_bench
          Declared:
            - signal clk, reset : bit
            - signal rpm : natural
            - signal forward : bit
          Hierarchy:
            - dut: entity work.propulsion
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd] 0:00:00.234514

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:20: interfaces must be separated by ';' (found ',')
libghdl: :27:2: object class keyword such as 'variable' is expected
libghdl: :28:2: 'begin' is expected instead of 'constant'
libghdl: :28:2: unexpected token 'constant' in a concurrent statement list
libghdl: :29:0: unexpected token 'begin' in a concurrent statement list
libghdl: :30:4: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd] 0:00:00.228809

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd'
Iir_Kind.Integer_Type_Definition
libghdl processing time:  184.004 us
DOM translation time:    2064.638 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_09(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd':
      Entities:
        - Name: inline_09
          File: inline_09.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_09.vhd
          Position: 28:13
          Entity: inline_09
          Declared:
            - signal clk, reset, trigger, test0, test1 : bit := 0
          Hierarchy:
            - process_3_h: process(...)
            - process_3_i: process(...)
            - process_3_j: process(...)
            - test_gen: process(...)
            - stimulus_3_h_i_j: process(...)
          Statements:
            ...
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd] 0:00:00.234230

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:20: ';' or ')' expected after interface
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:19: interfaces must be separated by ';' (found ',')
libghdl: :28:2: object class keyword such as 'variable' is expected
libghdl: :29:2: 'begin' is expected instead of "quantity"
libghdl: :29:11: '<=' is expected instead of "v_out"
libghdl: :29:16: ';' expected at end of signal assignment
libghdl: :29:16: (found: an identifier)
libghdl: :29:24: '<=' is expected instead of "i_out"
libghdl: :29:29: ';' expected at end of signal assignment
libghdl: :29:29: (found: an identifier)
libghdl: :29:38: '<=' is expected instead of "o"
libghdl: :30:0: unexpected token 'begin' in a concurrent statement list
libghdl: :31:8: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd] 0:00:00.237831

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 34
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 37
Iir_Kind.Integer_Type_Definition
libghdl processing time:  118.602 us
DOM translation time:    1547.628 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_17(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd':
      Entities:
        - Name: inline_17
          File: inline_17.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_17.vhd
          Position: 28:13
          Entity: inline_17
          Declared:
            - signal s, r, q, q_n : bit := 0
          Hierarchy:
            - check: process(...)
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd] 0:00:00.246158

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd'
Iir_Kind.Integer_Type_Definition
libghdl processing time:  150.702 us
DOM translation time:    783.015 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - d_ff(basic)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd':
      Entities:
        - Name: d_ff
          File: d_ff.vhd
          Position: 20:7
          Generics:
          Ports:
            - d, clk : in bit
            - q : out bit
          Declared:
          Statements:
          Architecures:
          - basic
      Architectures:
        - Name: basic
          File: d_ff.vhd
          Position: 24:13
          Entity: d_ff
          Declared:
          Hierarchy:
            - ff_behavior: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd] 0:00:00.225382

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd'
libghdl processing time:  75.402 us
DOM translation time:    324.406 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - and_or_inv()
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd':
      Entities:
        - Name: and_or_inv
          File: inline_03.vhd
          Position: 20:7
          Generics:
          Ports:
            - a1, a2, b1, b2 : in bit := 1
            - y : out bit
          Declared:
          Statements:
          Architecures:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd] 0:00:00.231079

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:22: interfaces must be separated by ';' (found ',')
libghdl: :28:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd] 0:00:00.228322

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd'
libghdl processing time:  85.502 us
DOM translation time:    819.914 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - edge_triggered_Dff(behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd':
      Entities:
        - Name: edge_triggered_Dff
          File: edge_triggered_Dff.vhd
          Position: 20:7
          Generics:
          Ports:
            - D : in bit
            - clk : in bit
            - clr : in bit
            - Q : out bit
          Declared:
          Statements:
          Architecures:
          - behavioral
      Architectures:
        - Name: behavioral
          File: edge_triggered_Dff.vhd
          Position: 27:13
          Entity: edge_triggered_Dff
          Declared:
          Hierarchy:
            - state_change: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd] 0:00:00.236644

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd'
libghdl processing time:  121.702 us
DOM translation time:    1885.233 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_S_R_flipflop(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd':
      Entities:
        - Name: tb_S_R_flipflop
          File: tb_S_R_flipflop.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: tb_S_R_flipflop.vhd
          Position: 24:13
          Entity: tb_S_R_flipflop
          Declared:
            - signal s, r : bit := 0
            - signal q, q_n : bit
          Hierarchy:
            - dut: entity work.S_R_flipflop
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd] 0:00:00.227127

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'scheduler') at line 47
Iir_Kind.Integer_Type_Definition
libghdl processing time:  184.503 us
DOM translation time:    2147.837 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - scheduler(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd':
      Entities:
        - Name: scheduler
          File: scheduler.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: scheduler.vhd
          Position: 24:13
          Entity: scheduler
          Declared:
            - constant scheduling_delay : delay_length := 5 ns
            - subtype request_type is ?????
            - type server_status_type is (........)
            - signal first_priority_request, first_normal_request, reset_request : request_type := 0
            - signal functional_request, equivalent_request : request_type
            - signal priority_waiting : boolean := false
            - signal server_status : server_status_type := busy
          Hierarchy:
            - functional_scheduler: block
            - equivalent_scheduler: block
                - scheduler: process(...)
            - stimulus: process(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd] 0:00:00.256463

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd'
libghdl processing time:  73.801 us
DOM translation time:    946.817 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd':
      Entities:
      Architectures:
        - Name: abstract
          File: inline_05.vhd
          Position: 20:13
          Entity: adder
          Declared:
          Hierarchy:
            - add_a_b: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd] 0:00:00.253462

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  108.202 us
DOM translation time:    967.617 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_10(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd':
      Entities:
        - Name: inline_10
          File: inline_10.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_10.vhd
          Position: 28:13
          Entity: inline_10
          Declared:
            - signal data : bit_vector(7 downto 0)
            - signal s : bit := 0
          Hierarchy:
            - process_3_l: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd] 0:00:00.278115

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd'
libghdl processing time:  257.504 us
DOM translation time:    4755.684 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - add_1(boolean_eqn)
        - buf4(basic)
        - counter(registered)
      Packages:
        - counter_types
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd':
      Entities:
        - Name: add_1
          File: counter.vhd
          Position: 33:7
          Generics:
          Ports:
            - d0, d1, d2, d3 : in bit
            - y0, y1, y2, y3 : out bit
          Declared:
          Statements:
          Architecures:
          - boolean_eqn
        - Name: buf4
          File: counter.vhd
          Position: 56:7
          Generics:
          Ports:
            - a0, a1, a2, a3 : in bit
            - y0, y1, y2, y3 : out bit
          Declared:
          Statements:
          Architecures:
          - basic
        - Name: counter
          File: counter.vhd
          Position: 78:7
          Generics:
          Ports:
            - clk, clr : in bit
            - q0, q1 : out digit
          Declared:
          Statements:
          Architecures:
          - registered
      Architectures:
        - Name: boolean_eqn
          File: counter.vhd
          Position: 39:13
          Entity: add_1
          Declared:
          Hierarchy:
          Statements:
            ...
            ...
            ...
            ...
        - Name: basic
          File: counter.vhd
          Position: 62:13
          Entity: buf4
          Declared:
          Hierarchy:
          Statements:
            ...
            ...
            ...
            ...
        - Name: registered
          File: counter.vhd
          Position: 85:13
          Entity: counter
          Declared:
            - signal current_val0, current_val1, next_val0, next_val1 : digit
          Hierarchy:
            - val0_reg: entity work.reg4
            - val1_reg: entity work.reg4
            - incr0: entity work.add_1
            - incr1: entity work.add_1
            - buf0: entity work.buf4
            - buf1: entity work.buf4
          Statements:
            ...
            ...
            ...
            ...
            ...
            ...
      Packages:
        - Name: counter_types
          File: counter.vhd
          Position: 22:8
          Declared:
          - subtype digit is ?????
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd] 0:00:00.236744

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'reset_gen') at line 42
libghdl processing time:  153.903 us
DOM translation time:    1041.118 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_15(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd':
      Entities:
        - Name: inline_15
          File: inline_15.vhd
          Position: 20:7
          Generics:
            - extended_reset : in boolean := false
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_15.vhd
          Position: 28:13
          Entity: inline_15
          Declared:
            - signal functional_reset, equivalent_reset : bit := 0
          Hierarchy:
            - block_3_r: block
            - block_3_s: block
                - reset_gen: process(...)
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd] 0:00:00.237020

Setup

Call

[gw0] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 39
DOM: Unknown name kind 'Aggregate'

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd] 0:00:00.230085

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd'
libghdl processing time:  162.202 us
DOM translation time:    1312.423 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - mux(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd':
      Entities:
        - Name: mux
          File: mux.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: mux.vhd
          Position: 23:13
          Entity: mux
          Declared:
            - constant prop_delay : time := 5 ns
            - signal a, b, sel, z : bit
          Hierarchy:
            - mux: process(...)
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd] 0:00:00.226411

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd'
[NOT IMPLEMENTED] Concurrent (selected) signal assignment (label: 'None') at line 28
libghdl processing time:  144.003 us
DOM translation time:    607.211 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - full_adder(truth_table)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd':
      Entities:
        - Name: full_adder
          File: full_adder.vhd
          Position: 20:7
          Generics:
          Ports:
            - a, b, c_in : in bit
            - s, c_out : out bit
          Declared:
          Statements:
          Architecures:
          - truth_table
      Architectures:
        - Name: truth_table
          File: full_adder.vhd
          Position: 25:13
          Entity: full_adder
          Declared:
          Hierarchy:
          Statements:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd] 0:00:00.225464

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'asym_delay') at line 40
libghdl processing time:  129.202 us
DOM translation time:    648.111 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_16(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd':
      Entities:
        - Name: inline_16
          File: inline_16.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_16.vhd
          Position: 28:13
          Entity: inline_16
          Declared:
            - constant Tpd_01 : time := 800 ps
            - constant Tpd_10 : time := 500 ps
            - signal a, z : bit
          Hierarchy:
            - stimulus: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd] 0:00:00.243513

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd'
libghdl processing time:  65.901 us
DOM translation time:    460.308 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - adder()
      Packages:
        - adder_types
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd':
      Entities:
        - Name: adder
          File: inline_02.vhd
          Position: 33:7
          Generics:
          Ports:
            - a, b : in word
            - sum : out word
          Declared:
          Statements:
          Architecures:
      Architectures:
      Packages:
        - Name: adder_types
          File: inline_02.vhd
          Position: 22:8
          Declared:
          - subtype word is ?????
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd] 0:00:00.233769

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd'
libghdl processing time:  114.502 us
DOM translation time:    1047.218 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - reg()
        - microprocessor(RTL)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd':
      Entities:
        - Name: reg
          File: microprocessor.vhd
          Position: 20:7
          Generics:
          Ports:
            - d : in bit_vector(7 downto 0)
            - q : out bit_vector(7 downto 0)
            - clk : in bit
          Declared:
          Statements:
          Architecures:
        - Name: microprocessor
          File: microprocessor.vhd
          Position: 30:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - RTL
      Architectures:
        - Name: RTL
          File: microprocessor.vhd
          Position: 35:13
          Entity: microprocessor
          Declared:
            - signal interrupt_req : bit
            - signal interrupt_level : bit_vector(2 downto 0)
            - signal carry_flag, negative_flag, overflow_flag, zero_flag : bit
            - signal program_status : bit_vector(7 downto 0)
            - signal clk_PSR : bit
          Hierarchy:
            - psr: entity work.reg
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd] 0:00:00.236709

Setup

Call

[gw0] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd'
DOM: Unknown name kind 'Aggregate'

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd] 0:00:00.241599

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd'
libghdl processing time:  99.001 us
DOM translation time:    594.411 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - clock_gen(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd':
      Entities:
        - Name: clock_gen
          File: clock_gen-2.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: clock_gen-2.vhd
          Position: 23:13
          Entity: clock_gen
          Declared:
            - constant T_pw : time := 10 ns
            - signal clk : bit
          Hierarchy:
            - clock_gen: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd] 0:00:00.231758

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd'
libghdl processing time:  127.002 us
DOM translation time:    1433.625 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_rom(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd':
      Entities:
        - Name: tb_rom
          File: tb_rom.vhd
          Position: 25:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: do_nothing
          File: tb_rom.vhd
          Position: 20:13
          Entity: ROM
          Declared:
          Hierarchy:
          Statements:
        - Name: test
          File: tb_rom.vhd
          Position: 29:13
          Entity: tb_rom
          Declared:
            - signal address : natural := 0
            - signal data : bit_vector(0 to 7)
            - signal enable : bit := 0
          Hierarchy:
            - dut: entity work.ROM
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd] 0:00:00.240118

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd'
libghdl processing time:  100.002 us
DOM translation time:    950.317 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - reg4(struct)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd':
      Entities:
        - Name: reg4
          File: reg4.vhd
          Position: 20:7
          Generics:
          Ports:
            - clk, clr, d0, d1, d2, d3 : in bit
            - q0, q1, q2, q3 : out bit
          Declared:
          Statements:
          Architecures:
          - struct
      Architectures:
        - Name: struct
          File: reg4.vhd
          Position: 27:13
          Entity: reg4
          Declared:
          Hierarchy:
            - bit0: entity work.edge_triggered_Dff
            - bit1: entity work.edge_triggered_Dff
            - bit2: entity work.edge_triggered_Dff
            - bit3: entity work.edge_triggered_Dff
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd] 0:00:00.238444

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd'
libghdl processing time:  91.102 us
DOM translation time:    721.712 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_11(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd':
      Entities:
        - Name: inline_11
          File: inline_11.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_11.vhd
          Position: 28:13
          Entity: inline_11
          Declared:
            - signal line_in, line_out : bit := 0
          Hierarchy:
            - transmission_line: process(...)
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd] 0:00:00.231527

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  132.402 us
DOM translation time:    698.113 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - program_ROM()
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd':
      Entities:
        - Name: program_ROM
          File: program_rom.vhd
          Position: 27:7
          Generics:
          Ports:
            - address : in std_ulogic_vector(14 downto 0)
            - data : out std_ulogic_vector(7 downto 0)
            - enable : in std_ulogic
          Declared:
          - subtype instruction_byte is ?????
          - type ???? is array(........) of .....
          - constant program : program_array := (None, None, None, None, None, others => None)
          Statements:
          Architecures:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd] 0:00:00.233217

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd'
libghdl processing time:  76.102 us
DOM translation time:    330.606 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - S_R_flipflop()
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd':
      Entities:
        - Name: S_R_flipflop
          File: S_R_flipflop-1.vhd
          Position: 20:7
          Generics:
          Ports:
            - s, r : in bit
            - q, q_n : out bit
          Declared:
          Statements:
            ...
          Architecures:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd] 0:00:00.240417

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd'
libghdl processing time:  130.502 us
DOM translation time:    1280.422 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - and_or_inv(primitive)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd':
      Entities:
        - Name: and_or_inv
          File: and_or_inv.vhd
          Position: 22:7
          Generics:
          Ports:
            - a1, a2, b1, b2 : in bit := 1
            - y : out bit
          Declared:
          Statements:
          Architecures:
          - primitive
      Architectures:
        - Name: primitive
          File: and_or_inv.vhd
          Position: 30:13
          Entity: and_or_inv
          Declared:
            - signal and_a, and_b : bit
            - signal or_a_b : bit
          Hierarchy:
            - and_gate_a: process(...)
            - and_gate_b: process(...)
            - or_gate: process(...)
            - inv: process(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd] 0:00:00.237992

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd'
libghdl processing time:  97.702 us
DOM translation time:    650.111 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - clock_gen(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd':
      Entities:
        - Name: clock_gen
          File: clock_gen-1.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: clock_gen-1.vhd
          Position: 23:13
          Entity: clock_gen
          Declared:
            - constant T_pw : time := 10 ns
            - signal clk : bit
          Hierarchy:
            - clock_gen: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd] 0:00:00.233542

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd'
libghdl processing time:  91.002 us
DOM translation time:    906.515 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_13(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd':
      Entities:
        - Name: inline_13
          File: inline_13.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_13.vhd
          Position: 30:13
          Entity: inline_13
          Declared:
            - signal s : std_ulogic
          Hierarchy:
            - process_3_o: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd] 0:00:00.231644

Setup

Call

[gw1] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd'
DOM: Unknown name kind 'Aggregate'

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd] 0:00:00.241987

Setup

Call

[gw0] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd'
DOM: Unknown name kind 'Aggregate'

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd] 0:00:00.280012

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd'
Iir_Kind.Integer_Type_Definition
Iir_Kind.Floating_Type_Definition
libghdl processing time:  86.701 us
DOM translation time:    986.617 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - mux2(behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd':
      Entities:
        - Name: mux2
          File: mux2.vhd
          Position: 20:7
          Generics:
          Ports:
            - a, b, sel : in bit
            - z : out bit
          Declared:
          Statements:
          Architecures:
          - behavioral
      Architectures:
        - Name: behavioral
          File: mux2.vhd
          Position: 27:13
          Entity: mux2
          Declared:
            - constant prop_delay : time := 2 ns
          Hierarchy:
            - slick_mux: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd] 0:00:00.226433

Setup

Call

[gw1] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd'
DOM: Unknown name kind 'Aggregate'

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd] 0:00:00.234270

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd'
[NOT IMPLEMENTED] Concurrent (selected) signal assignment (label: 'alu') at line 83
Iir_Kind.Integer_Type_Definition
[NOT IMPLEMENTED] Bit String Literal not supported yet
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  386.807 us
DOM translation time:    2919.651 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - alu(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd':
      Entities:
        - Name: alu
          File: alu.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: alu.vhd
          Position: 24:13
          Entity: alu
          Declared:
            - constant Tpd : delay_length := 2 ns
            - function " return bit_vector
            - function " return bit_vector
            - type alu_function_type is (........)
            - signal alu_function : alu_function_type := alu_pass_a
            - signal a, b : bit_vector(15 downto 0)
            - signal functional_result, equivalent_result : bit_vector(15 downto 0)
          Hierarchy:
            - functional_alu: block
            - equivalent_alu: block
                - alu: process(...)
            - stimulus: process(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd] 0:00:00.228290

Setup

Call

[gw1] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd'
DOM: Unknown statement of kind 'While_Loop_Statement' in process 'cpu' at /home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd:44:4.

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd] 0:00:00.234981

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd'
libghdl processing time:  299.105 us
DOM translation time:    1127.220 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - FIFO()
        - inline_20(test)
      Packages:
        - inline_20_types
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd':
      Entities:
        - Name: FIFO
          File: inline_20.vhd
          Position: 38:7
          Generics:
          Ports:
            - status : out FIFO_status
            - other_ports : out bit
          Declared:
          Statements:
          Architecures:
        - Name: inline_20
          File: inline_20.vhd
          Position: 47:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_20.vhd
          Position: 57:13
          Entity: inline_20
          Declared:
            - signal start_flush, end_flush, DMA_buffer_full, DMA_buffer_empty : bit
          Hierarchy:
            - dma_buffer: entity work.FIFO
          Statements:
            ...
      Packages:
        - Name: inline_20_types
          File: inline_20.vhd
          Position: 20:8
          Declared:
          - type FIFO_status is record ..... end record
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd] 0:00:00.234847

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd'
libghdl processing time:  142.103 us
DOM translation time:    1101.719 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - DRAM_controller(fpld)
        - inline_18(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd':
      Entities:
        - Name: DRAM_controller
          File: inline_18.vhd
          Position: 22:7
          Generics:
          Ports:
            - rd, wr, mem : in bit
            - ras, cas, we, ready : out bit
          Declared:
          Statements:
          Architecures:
          - fpld
        - Name: inline_18
          File: inline_18.vhd
          Position: 41:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: fpld
          File: inline_18.vhd
          Position: 33:13
          Entity: DRAM_controller
          Declared:
          Hierarchy:
          Statements:
        - Name: test
          File: inline_18.vhd
          Position: 49:13
          Entity: inline_18
          Declared:
          Hierarchy:
            - block_4_a: block
                - main_mem_controller: entity work.DRAM_controller
            - block_4_b: block
                - main_mem_controller: entity work.DRAM_controller
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd] 0:00:00.233941

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'zmux') at line 40
Iir_Kind.Integer_Type_Definition
libghdl processing time:  252.904 us
DOM translation time:    2268.040 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - zmux(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd':
      Entities:
        - Name: zmux
          File: zmux.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: zmux.vhd
          Position: 26:13
          Entity: zmux
          Declared:
            - signal sel0, sel1, d0, d1, d2, d3 : bit := 0
            - signal functional_z, equivalent_z : bit
          Hierarchy:
            - functional_mux: block
            - equivalent_mux: block
                - zmux: process(...)
            - stimulus: all_possible_values(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd] 0:00:00.232949

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd'
libghdl processing time:  137.702 us
DOM translation time:    1562.427 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_12(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd':
      Entities:
        - Name: inline_12
          File: inline_12.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_12.vhd
          Position: 28:13
          Entity: inline_12
          Declared:
            - signal top_a, bottom_a : bit := 0
            - signal top_y, bottom_y : bit
          Hierarchy:
            - block_3_m: block
                - inv: process(...)
            - block_3_n: block
                - inv: process(...)
            - stimulus_3_m_n: process(...)
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd] 0:00:00.247979

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd'
Iir_Kind.Integer_Type_Definition
libghdl processing time:  326.906 us
DOM translation time:    1381.424 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_06(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd':
      Entities:
        - Name: inline_06
          File: inline_06.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_06.vhd
          Position: 28:13
          Entity: inline_06
          Declared:
            - signal y : bit := 0
            - signal or_a_b : bit := 0
            - signal clk : bit := 0
          Hierarchy:
            - process_3_a: process(...)
            - stimulus_3_a: process(...)
            - process_3_b: process(...)
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd] 0:00:00.225934

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd'
libghdl processing time:  150.103 us
DOM translation time:    2287.940 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - mux4(functional)
        - inline_22(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd':
      Entities:
        - Name: mux4
          File: inline_22.vhd
          Position: 22:7
          Generics:
          Ports:
            - i0, i1, i2, i3, sel0, sel1 : in bit
            - z : out bit
          Declared:
          Statements:
          Architecures:
          - functional
        - Name: inline_22
          File: inline_22.vhd
          Position: 53:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: functional
          File: inline_22.vhd
          Position: 33:13
          Entity: mux4
          Declared:
          Hierarchy:
            - out_select: process(...)
          Statements:
            ...
        - Name: test
          File: inline_22.vhd
          Position: 61:13
          Entity: inline_22
          Declared:
            - signal select_line, line0, line1, result_line : bit
          Hierarchy:
            - a_mux: entity work.mux4
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd] 0:00:00.231460

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd'
libghdl processing time:  88.902 us
DOM translation time:    865.215 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - ROM()
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd':
      Entities:
        - Name: ROM
          File: rom.vhd
          Position: 20:7
          Generics:
          Ports:
            - address : in natural
            - data : out bit_vector(0 to 7)
            - enable : in bit
          Declared:
          Statements:
            ...
          Architecures:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd] 0:00:00.226645

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd'
Iir_Kind.Integer_Type_Definition
libghdl processing time:  164.503 us
DOM translation time:    1105.219 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_14(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd':
      Entities:
        - Name: inline_14
          File: inline_14.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_14.vhd
          Position: 28:13
          Entity: inline_14
          Declared:
            - signal PC, functional_next_PC, equivalent_next_PC : integer := 0
          Hierarchy:
            - block_3_p: block
            - block_3_q: block
                - pc_incr: process(...)
            - stimulus: process(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd] 0:00:00.241332

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 24
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 27
libghdl processing time:  135.602 us
DOM translation time:    1970.535 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_S_R_flipflop(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd':
      Entities:
        - Name: tb_S_R_flipflop
          File: tb_S_R_flipflop-1.vhd
          Position: 33:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: functional
          File: tb_S_R_flipflop-1.vhd
          Position: 20:13
          Entity: S_R_flipflop
          Declared:
          Hierarchy:
          Statements:
        - Name: test
          File: tb_S_R_flipflop-1.vhd
          Position: 37:13
          Entity: tb_S_R_flipflop
          Declared:
            - signal s, r : bit := 0
            - signal q, q_n : bit
          Hierarchy:
            - dut: entity work.S_R_flipflop
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd] 0:00:00.231011

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd'
libghdl processing time:  138.202 us
DOM translation time:    1540.527 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_edge_triggered_Dff(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd':
      Entities:
        - Name: tb_edge_triggered_Dff
          File: tb_edge_triggered_Dff.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: tb_edge_triggered_Dff.vhd
          Position: 24:13
          Entity: tb_edge_triggered_Dff
          Declared:
            - signal D, clk, clr, Q : bit := 0
          Hierarchy:
            - dut: entity work.edge_triggered_Dff
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd] 0:00:00.229512

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd'
libghdl processing time:  160.802 us
DOM translation time:    971.817 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_and_or_inv(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd':
      Entities:
        - Name: tb_and_or_inv
          File: tb_and_or_inv.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: tb_and_or_inv.vhd
          Position: 24:13
          Entity: tb_and_or_inv
          Declared:
            - signal a1, a2, b1, b2, y : bit
          Hierarchy:
            - dut: entity work.and_or_inv
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd] 0:00:00.220379

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd'
libghdl processing time:  117.503 us
DOM translation time:    825.114 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_mux2(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd':
      Entities:
        - Name: tb_mux2
          File: tb_mux2.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: tb_mux2.vhd
          Position: 23:13
          Entity: tb_mux2
          Declared:
            - signal a, b, sel, z : bit
          Hierarchy:
            - dut: entity work.mux2
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd] 0:00:00.224311

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd'
libghdl processing time:  52.300 us
DOM translation time:    67.902 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - inline_19
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: inline_19
          File: inline_19.vhd
          Position: 20:8
          Declared:
          - subtype digit is ?????
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd] 0:00:00.240110

Setup

Call

[gw0] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd'
Iir_Kind.Integer_Type_Definition
DOM: Unknown name kind 'Aggregate'

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd] 0:00:00.230036

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd'
libghdl processing time:  112.802 us
DOM translation time:    1024.218 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - asym_delay(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd':
      Entities:
        - Name: asym_delay
          File: asym_delay.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: asym_delay.vhd
          Position: 25:13
          Entity: asym_delay
          Declared:
            - signal a, z : bit
          Hierarchy:
            - asym_delay: process(...)
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd] 0:00:00.232815

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd'
libghdl processing time:  64.101 us
DOM translation time:    310.005 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - adder()
      Packages:
        - adder_types
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd':
      Entities:
        - Name: adder
          File: inline_01.vhd
          Position: 33:7
          Generics:
          Ports:
            - a : in word
            - b : in word
            - sum : out word
          Declared:
          Statements:
          Architecures:
      Architectures:
      Packages:
        - Name: adder_types
          File: inline_01.vhd
          Position: 22:8
          Declared:
          - subtype word is ?????
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd] 0:00:00.280913

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 30
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'None') at line 33
libghdl processing time:  115.802 us
DOM translation time:    885.016 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - S_R_flipflop(functional)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd':
      Entities:
        - Name: S_R_flipflop
          File: S_R_flipflop.vhd
          Position: 20:7
          Generics:
          Ports:
            - s, r : in bit
            - q, q_n : out bit
          Declared:
          Statements:
          Architecures:
          - functional
      Architectures:
        - Name: functional
          File: S_R_flipflop.vhd
          Position: 26:13
          Entity: S_R_flipflop
          Declared:
          Hierarchy:
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd] 0:00:00.293834

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd'
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'zmux') at line 40
Iir_Kind.Integer_Type_Definition
libghdl processing time:  192.904 us
DOM translation time:    2408.842 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - zmux(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd':
      Entities:
        - Name: zmux
          File: zmux-1.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: zmux-1.vhd
          Position: 26:13
          Entity: zmux
          Declared:
            - signal sel0, sel1, d0, d1, d2, d3 : bit := 0
            - signal functional_z, equivalent_z : bit
          Hierarchy:
            - functional_mux: block
            - equivalent_mux: block
                - zmux: process(...)
            - stimulus: all_possible_values(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd] 0:00:00.298675

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd'
libghdl processing time:  186.004 us
DOM translation time:    3336.358 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_07(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd':
      Entities:
        - Name: inline_07
          File: inline_07.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_07.vhd
          Position: 30:13
          Entity: inline_07
          Declared:
            - signal clk, d : std_ulogic
            - constant Tpw_clk : delay_length := 10 ns
            - constant Tsu : delay_length := 4 ns
          Hierarchy:
            - process_3_c: process(...)
            - process_3_d: process(...)
            - process_3_e: process(...)
            - stimulus_3_c_d: process(...)
          Statements:
            ...
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd] 0:00:00.315319

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd'
libghdl processing time:  158.303 us
DOM translation time:    3035.853 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_and2(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd':
      Entities:
        - Name: tb_and2
          File: tb_and2.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: tb_and2.vhd
          Position: 26:13
          Entity: tb_and2
          Declared:
            - signal a, b : std_ulogic := 0
            - signal y : std_ulogic
          Hierarchy:
            - dut: entity work.and2
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd] 0:00:00.239698

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd'
libghdl processing time:  108.502 us
DOM translation time:    772.913 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - clock_gen(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd':
      Entities:
        - Name: clock_gen
          File: clock_gen.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: clock_gen.vhd
          Position: 23:13
          Entity: clock_gen
          Declared:
            - constant T_pw : time := 10 ns
            - signal clk : bit
          Hierarchy:
            - clock_gen: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd] 0:00:00.232193

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd'
libghdl processing time:  93.002 us
DOM translation time:    718.212 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - tb_counter(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd':
      Entities:
        - Name: tb_counter
          File: tb_counter.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: tb_counter.vhd
          Position: 26:13
          Entity: tb_counter
          Declared:
            - signal clk, clr : bit := 0
            - signal q0, q1 : digit
          Hierarchy:
            - dut: entity work.counter
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd] 0:00:00.244033

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd'
DOM: Error raised in libghdl.
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:21: interfaces must be separated by ';' (found ',')
libghdl: :28:12: ':' expected after interface identifier
libghdl: :28:12: (found: an identifier)
libghdl: :28:18: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "vin2"
libghdl: :33:15: ';' expected at end of signal assignment
libghdl: :33:15: (found: an identifier)
libghdl: :33:23: '<=' is expected instead of "in2"
libghdl: :33:26: ';' expected at end of signal assignment
libghdl: :33:26: (found: 'to')
libghdl: :33:27: unexpected token 'to' in a concurrent statement list
libghdl: :34:11: '<=' is expected instead of "vout"
libghdl: :34:15: ';' expected at end of signal assignment
libghdl: :34:15: (found: an identifier)
libghdl: :34:23: '<=' is expected instead of "iout"
libghdl: :34:27: ';' expected at end of signal assignment
libghdl: :34:27: (found: an identifier)
libghdl: :34:36: '<=' is expected instead of "output"
libghdl: :34:42: ';' expected at end of signal assignment
libghdl: :34:42: (found: 'to')
libghdl: :34:43: unexpected token 'to' in a concurrent statement list
libghdl: :36:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:6: '==' is not the vhdl equality, replaced by '='
libghdl: :50:18: ':' expected after interface identifier
libghdl: :50:18: (found: an identifier)
libghdl: :50:24: ';' or ')' expected after interface
libghdl: :51:12: ':' expected after interface identifier
libghdl: :51:12: (found: an identifier)
libghdl: :51:18: ';' or ')' expected after interface
libghdl: :56:2: object class keyword such as 'variable' is expected
libghdl: :57:2: 'begin' is expected instead of "quantity"
libghdl: :57:11: '<=' is expected instead of "vout"
libghdl: :57:15: ';' expected at end of signal assignment
libghdl: :57:15: (found: an identifier)
libghdl: :57:23: '<=' is expected instead of "iout"
libghdl: :57:27: ';' expected at end of signal assignment
libghdl: :57:27: (found: an identifier)
libghdl: :57:36: '<=' is expected instead of "output"
libghdl: :57:42: ';' expected at end of signal assignment
libghdl: :57:42: (found: 'to')
libghdl: :57:43: unexpected token 'to' in a concurrent statement list
libghdl: :59:0: unexpected token 'begin' in a concurrent statement list
libghdl: :60:6: '==' is not the vhdl equality, replaced by '='
libghdl: :75:11: ':' expected after interface identifier
libghdl: :75:11: (found: an identifier)
libghdl: :75:16: ';' or ')' expected after interface
libghdl: :76:11: ':' expected after interface identifier
libghdl: :76:11: (found: an identifier)
libghdl: :76:17: ';' or ')' expected after interface
libghdl: :80:3: object class keyword such as 'variable' is expected
libghdl: :81:3: 'begin' is expected instead of "quantity"
libghdl: :81:12: '<=' is expected instead of "vout"
libghdl: :81:16: ';' expected at end of signal assignment
libghdl: :81:16: (found: an identifier)
libghdl: :81:24: '<=' is expected instead of "iout"
libghdl: :81:28: ';' expected at end of signal assignment
libghdl: :81:28: (found: an identifier)
libghdl: :81:37: '<=' is expected instead of "output"
libghdl: :81:43: ';' expected at end of signal assignment
libghdl: :81:43: (found: 'to')
libghdl: :81:44: unexpected token 'to' in a concurrent statement list
libghdl: :82:1: unexpected token 'constant' in a concurrent statement list
libghdl: :83:0: unexpected token 'begin' in a concurrent statement list
libghdl: :84:21: if/use is an AMS-VHDL statement
libghdl: :85:7: '==' is not the vhdl equality, replaced by '='
libghdl: :85:7: '==' expected after expression
libghdl: :85:7: (found: '=')
libghdl: :85:7: unexpected token '=' in a primary
libghdl: :85:6: ';' is expected instead of '='
libghdl: :85:7: unexpected token '=' in a simultaneous statement list
libghdl: :87:7: '==' is not the vhdl equality, replaced by '='
libghdl: :87:7: '==' expected after expression
libghdl: :87:7: (found: '=')
libghdl: :87:7: unexpected token '=' in a primary
libghdl: :87:6: ';' is expected instead of '='
libghdl: :87:7: unexpected token '=' in a simultaneous statement list
libghdl: :89:7: '==' is not the vhdl equality, replaced by '='
libghdl: :89:7: '==' expected after expression
libghdl: :89:7: (found: '=')
libghdl: :89:7: unexpected token '=' in a primary
libghdl: :89:6: ';' is expected instead of '='
libghdl: :89:7: unexpected token '=' in a simultaneous statement list
libghdl: :91:7: '<=' is expected instead of 'on'
libghdl: :91:7: unexpected token 'on' in a primary
libghdl: :91:6: ';' expected at end of signal assignment
libghdl: :91:6: (found: 'on')
libghdl: :91:7: unexpected token 'on' in a concurrent statement list
libghdl: :119:18: ':' expected after interface identifier
libghdl: :119:18: (found: an identifier)
libghdl: :119:23: ';' or ')' expected after interface
libghdl: :120:12: ':' expected after interface identifier
libghdl: :120:12: (found: an identifier)
libghdl: :120:18: ';' or ')' expected after interface
libghdl: :124:2: object class keyword such as 'variable' is expected
libghdl: :125:2: 'begin' is expected instead of "quantity"
libghdl: :125:11: '<=' is expected instead of "vout"
libghdl: :125:15: ';' expected at end of signal assignment
libghdl: :125:15: (found: an identifier)
libghdl: :125:23: '<=' is expected instead of "iout"
libghdl: :125:27: ';' expected at end of signal assignment
libghdl: :125:27: (found: an identifier)
libghdl: :125:36: '<=' is expected instead of "output"
libghdl: :125:42: ';' expected at end of signal assignment
libghdl: :125:42: (found: 'to')
libghdl: :125:43: unexpected token 'to' in a concurrent statement list
libghdl: :127:10: '<=' is expected instead of "vin_temp"
libghdl: :127:18: ';' expected at end of signal assignment
libghdl: :127:18: (found: ':')
libghdl: :127:19: unexpected token ':' in a concurrent statement list
libghdl: :128:1: unexpected token 'constant' in a concurrent statement list
libghdl: :129:1: unexpected token 'constant' in a concurrent statement list
libghdl: :130:1: unexpected token 'constant' in a concurrent statement list
libghdl: :131:1: unexpected token 'constant' in a concurrent statement list
libghdl: :132:0: unexpected token 'begin' in a concurrent statement list
libghdl: :133:10: '==' is not the vhdl equality, replaced by '='
libghdl: :134:6: '==' is not the vhdl equality, replaced by '='
libghdl: :134:6: '<=' is expected instead of '='
libghdl: :134:6: unexpected token '=' in a primary
libghdl: :147:17: ':' expected after interface identifier
libghdl: :147:17: (found: an identifier)
libghdl: :147:26: ';' or ')' expected after interface
libghdl: :148:17: ':' expected after interface identifier
libghdl: :148:17: (found: an identifier)
libghdl: :148:24: ';' or ')' expected after interface
libghdl: :149:17: ':' expected after interface identifier
libghdl: :149:17: (found: an identifier)
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd] 0:00:00.235815

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd'
libghdl processing time:  118.602 us
DOM translation time:    1193.821 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - and2(detailed_delay)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd':
      Entities:
        - Name: and2
          File: and2.vhd
          Position: 22:7
          Generics:
          Ports:
            - a, b : in std_ulogic
            - y : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - detailed_delay
      Architectures:
        - Name: detailed_delay
          File: and2.vhd
          Position: 28:13
          Entity: and2
          Declared:
            - signal result : std_ulogic
          Hierarchy:
            - gate: process(...)
            - delay: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd] 0:00:00.233593

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd'
DOM: Error raised in libghdl.
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:21: interfaces must be separated by ';' (found ',')
libghdl: :28:12: ':' expected after interface identifier
libghdl: :28:12: (found: an identifier)
libghdl: :28:18: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "vin2"
libghdl: :33:15: ';' expected at end of signal assignment
libghdl: :33:15: (found: an identifier)
libghdl: :33:23: '<=' is expected instead of "in2"
libghdl: :33:26: ';' expected at end of signal assignment
libghdl: :33:26: (found: 'to')
libghdl: :33:27: unexpected token 'to' in a concurrent statement list
libghdl: :34:11: '<=' is expected instead of "vout"
libghdl: :34:15: ';' expected at end of signal assignment
libghdl: :34:15: (found: an identifier)
libghdl: :34:23: '<=' is expected instead of "iout"
libghdl: :34:27: ';' expected at end of signal assignment
libghdl: :34:27: (found: an identifier)
libghdl: :34:36: '<=' is expected instead of "output"
libghdl: :34:42: ';' expected at end of signal assignment
libghdl: :34:42: (found: 'to')
libghdl: :34:43: unexpected token 'to' in a concurrent statement list
libghdl: :36:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:6: '==' is not the vhdl equality, replaced by '='
libghdl: :50:18: ':' expected after interface identifier
libghdl: :50:18: (found: an identifier)
libghdl: :50:24: ';' or ')' expected after interface
libghdl: :51:12: ':' expected after interface identifier
libghdl: :51:12: (found: an identifier)
libghdl: :51:18: ';' or ')' expected after interface
libghdl: :56:2: object class keyword such as 'variable' is expected
libghdl: :57:2: 'begin' is expected instead of "quantity"
libghdl: :57:11: '<=' is expected instead of "vout"
libghdl: :57:15: ';' expected at end of signal assignment
libghdl: :57:15: (found: an identifier)
libghdl: :57:23: '<=' is expected instead of "iout"
libghdl: :57:27: ';' expected at end of signal assignment
libghdl: :57:27: (found: an identifier)
libghdl: :57:36: '<=' is expected instead of "output"
libghdl: :57:42: ';' expected at end of signal assignment
libghdl: :57:42: (found: 'to')
libghdl: :57:43: unexpected token 'to' in a concurrent statement list
libghdl: :59:0: unexpected token 'begin' in a concurrent statement list
libghdl: :60:6: '==' is not the vhdl equality, replaced by '='
libghdl: :75:11: ':' expected after interface identifier
libghdl: :75:11: (found: an identifier)
libghdl: :75:16: ';' or ')' expected after interface
libghdl: :76:11: ':' expected after interface identifier
libghdl: :76:11: (found: an identifier)
libghdl: :76:17: ';' or ')' expected after interface
libghdl: :80:3: object class keyword such as 'variable' is expected
libghdl: :81:3: 'begin' is expected instead of "quantity"
libghdl: :81:12: '<=' is expected instead of "vout"
libghdl: :81:16: ';' expected at end of signal assignment
libghdl: :81:16: (found: an identifier)
libghdl: :81:24: '<=' is expected instead of "iout"
libghdl: :81:28: ';' expected at end of signal assignment
libghdl: :81:28: (found: an identifier)
libghdl: :81:37: '<=' is expected instead of "output"
libghdl: :81:43: ';' expected at end of signal assignment
libghdl: :81:43: (found: 'to')
libghdl: :81:44: unexpected token 'to' in a concurrent statement list
libghdl: :82:1: unexpected token 'constant' in a concurrent statement list
libghdl: :83:0: unexpected token 'begin' in a concurrent statement list
libghdl: :84:21: if/use is an AMS-VHDL statement
libghdl: :85:7: '==' is not the vhdl equality, replaced by '='
libghdl: :85:7: '==' expected after expression
libghdl: :85:7: (found: '=')
libghdl: :85:7: unexpected token '=' in a primary
libghdl: :85:6: ';' is expected instead of '='
libghdl: :85:7: unexpected token '=' in a simultaneous statement list
libghdl: :87:7: '==' is not the vhdl equality, replaced by '='
libghdl: :87:7: '==' expected after expression
libghdl: :87:7: (found: '=')
libghdl: :87:7: unexpected token '=' in a primary
libghdl: :87:6: ';' is expected instead of '='
libghdl: :87:7: unexpected token '=' in a simultaneous statement list
libghdl: :89:7: '==' is not the vhdl equality, replaced by '='
libghdl: :89:7: '==' expected after expression
libghdl: :89:7: (found: '=')
libghdl: :89:7: unexpected token '=' in a primary
libghdl: :89:6: ';' is expected instead of '='
libghdl: :89:7: unexpected token '=' in a simultaneous statement list
libghdl: :91:7: '<=' is expected instead of 'on'
libghdl: :91:7: unexpected token 'on' in a primary
libghdl: :91:6: ';' expected at end of signal assignment
libghdl: :91:6: (found: 'on')
libghdl: :91:7: unexpected token 'on' in a concurrent statement list
libghdl: :119:18: ':' expected after interface identifier
libghdl: :119:18: (found: an identifier)
libghdl: :119:23: ';' or ')' expected after interface
libghdl: :120:12: ':' expected after interface identifier
libghdl: :120:12: (found: an identifier)
libghdl: :120:18: ';' or ')' expected after interface
libghdl: :124:2: object class keyword such as 'variable' is expected
libghdl: :125:2: 'begin' is expected instead of "quantity"
libghdl: :125:11: '<=' is expected instead of "vout"
libghdl: :125:15: ';' expected at end of signal assignment
libghdl: :125:15: (found: an identifier)
libghdl: :125:23: '<=' is expected instead of "iout"
libghdl: :125:27: ';' expected at end of signal assignment
libghdl: :125:27: (found: an identifier)
libghdl: :125:36: '<=' is expected instead of "output"
libghdl: :125:42: ';' expected at end of signal assignment
libghdl: :125:42: (found: 'to')
libghdl: :125:43: unexpected token 'to' in a concurrent statement list
libghdl: :127:10: '<=' is expected instead of "vin_temp"
libghdl: :127:18: ';' expected at end of signal assignment
libghdl: :127:18: (found: ':')
libghdl: :127:19: unexpected token ':' in a concurrent statement list
libghdl: :128:1: unexpected token 'constant' in a concurrent statement list
libghdl: :129:1: unexpected token 'constant' in a concurrent statement list
libghdl: :130:1: unexpected token 'constant' in a concurrent statement list
libghdl: :131:1: unexpected token 'constant' in a concurrent statement list
libghdl: :132:0: unexpected token 'begin' in a concurrent statement list
libghdl: :133:10: '==' is not the vhdl equality, replaced by '='
libghdl: :134:6: '==' is not the vhdl equality, replaced by '='
libghdl: :134:6: '<=' is expected instead of '='
libghdl: :134:6: unexpected token '=' in a primary
libghdl: :149:17: ':' expected after interface identifier
libghdl: :149:17: (found: an identifier)
libghdl: :149:26: ';' or ')' expected after interface
libghdl: :150:17: ':' expected after interface identifier
libghdl: :150:17: (found: an identifier)
libghdl: :150:24: ';' or ')' expected after interface
libghdl: :151:17: ':' expected after interface identifier
libghdl: :151:17: (found: an identifier)
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd] 0:00:00.226249

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd'
libghdl processing time:  55.601 us
DOM translation time:    70.802 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - top_level()
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd':
      Entities:
        - Name: top_level
          File: inline_04.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd] 0:00:00.232110

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd'
DOM: Error raised in libghdl.
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:21: interfaces must be separated by ';' (found ',')
libghdl: :28:12: ':' expected after interface identifier
libghdl: :28:12: (found: an identifier)
libghdl: :28:18: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "vin2"
libghdl: :33:15: ';' expected at end of signal assignment
libghdl: :33:15: (found: an identifier)
libghdl: :33:23: '<=' is expected instead of "in2"
libghdl: :33:26: ';' expected at end of signal assignment
libghdl: :33:26: (found: 'to')
libghdl: :33:27: unexpected token 'to' in a concurrent statement list
libghdl: :34:11: '<=' is expected instead of "vout"
libghdl: :34:15: ';' expected at end of signal assignment
libghdl: :34:15: (found: an identifier)
libghdl: :34:23: '<=' is expected instead of "iout"
libghdl: :34:27: ';' expected at end of signal assignment
libghdl: :34:27: (found: an identifier)
libghdl: :34:36: '<=' is expected instead of "output"
libghdl: :34:42: ';' expected at end of signal assignment
libghdl: :34:42: (found: 'to')
libghdl: :34:43: unexpected token 'to' in a concurrent statement list
libghdl: :36:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:6: '==' is not the vhdl equality, replaced by '='
libghdl: :50:18: ':' expected after interface identifier
libghdl: :50:18: (found: an identifier)
libghdl: :50:24: ';' or ')' expected after interface
libghdl: :51:12: ':' expected after interface identifier
libghdl: :51:12: (found: an identifier)
libghdl: :51:18: ';' or ')' expected after interface
libghdl: :56:2: object class keyword such as 'variable' is expected
libghdl: :57:2: 'begin' is expected instead of "quantity"
libghdl: :57:11: '<=' is expected instead of "vout"
libghdl: :57:15: ';' expected at end of signal assignment
libghdl: :57:15: (found: an identifier)
libghdl: :57:23: '<=' is expected instead of "iout"
libghdl: :57:27: ';' expected at end of signal assignment
libghdl: :57:27: (found: an identifier)
libghdl: :57:36: '<=' is expected instead of "output"
libghdl: :57:42: ';' expected at end of signal assignment
libghdl: :57:42: (found: 'to')
libghdl: :57:43: unexpected token 'to' in a concurrent statement list
libghdl: :59:0: unexpected token 'begin' in a concurrent statement list
libghdl: :60:6: '==' is not the vhdl equality, replaced by '='
libghdl: :75:11: ':' expected after interface identifier
libghdl: :75:11: (found: an identifier)
libghdl: :75:16: ';' or ')' expected after interface
libghdl: :76:11: ':' expected after interface identifier
libghdl: :76:11: (found: an identifier)
libghdl: :76:17: ';' or ')' expected after interface
libghdl: :80:3: object class keyword such as 'variable' is expected
libghdl: :81:3: 'begin' is expected instead of "quantity"
libghdl: :81:12: '<=' is expected instead of "vout"
libghdl: :81:16: ';' expected at end of signal assignment
libghdl: :81:16: (found: an identifier)
libghdl: :81:24: '<=' is expected instead of "iout"
libghdl: :81:28: ';' expected at end of signal assignment
libghdl: :81:28: (found: an identifier)
libghdl: :81:37: '<=' is expected instead of "output"
libghdl: :81:43: ';' expected at end of signal assignment
libghdl: :81:43: (found: 'to')
libghdl: :81:44: unexpected token 'to' in a concurrent statement list
libghdl: :82:1: unexpected token 'constant' in a concurrent statement list
libghdl: :83:0: unexpected token 'begin' in a concurrent statement list
libghdl: :84:21: if/use is an AMS-VHDL statement
libghdl: :85:7: '==' is not the vhdl equality, replaced by '='
libghdl: :85:7: '==' expected after expression
libghdl: :85:7: (found: '=')
libghdl: :85:7: unexpected token '=' in a primary
libghdl: :85:6: ';' is expected instead of '='
libghdl: :85:7: unexpected token '=' in a simultaneous statement list
libghdl: :87:7: '==' is not the vhdl equality, replaced by '='
libghdl: :87:7: '==' expected after expression
libghdl: :87:7: (found: '=')
libghdl: :87:7: unexpected token '=' in a primary
libghdl: :87:6: ';' is expected instead of '='
libghdl: :87:7: unexpected token '=' in a simultaneous statement list
libghdl: :89:7: '==' is not the vhdl equality, replaced by '='
libghdl: :89:7: '==' expected after expression
libghdl: :89:7: (found: '=')
libghdl: :89:7: unexpected token '=' in a primary
libghdl: :89:6: ';' is expected instead of '='
libghdl: :89:7: unexpected token '=' in a simultaneous statement list
libghdl: :91:7: '<=' is expected instead of 'on'
libghdl: :91:7: unexpected token 'on' in a primary
libghdl: :91:6: ';' expected at end of signal assignment
libghdl: :91:6: (found: 'on')
libghdl: :91:7: unexpected token 'on' in a concurrent statement list
libghdl: :119:18: ':' expected after interface identifier
libghdl: :119:18: (found: an identifier)
libghdl: :119:23: ';' or ')' expected after interface
libghdl: :120:12: ':' expected after interface identifier
libghdl: :120:12: (found: an identifier)
libghdl: :120:18: ';' or ')' expected after interface
libghdl: :124:2: object class keyword such as 'variable' is expected
libghdl: :125:2: 'begin' is expected instead of "quantity"
libghdl: :125:11: '<=' is expected instead of "vout"
libghdl: :125:15: ';' expected at end of signal assignment
libghdl: :125:15: (found: an identifier)
libghdl: :125:23: '<=' is expected instead of "iout"
libghdl: :125:27: ';' expected at end of signal assignment
libghdl: :125:27: (found: an identifier)
libghdl: :125:36: '<=' is expected instead of "output"
libghdl: :125:42: ';' expected at end of signal assignment
libghdl: :125:42: (found: 'to')
libghdl: :125:43: unexpected token 'to' in a concurrent statement list
libghdl: :127:10: '<=' is expected instead of "vin_temp"
libghdl: :127:18: ';' expected at end of signal assignment
libghdl: :127:18: (found: ':')
libghdl: :127:19: unexpected token ':' in a concurrent statement list
libghdl: :128:1: unexpected token 'constant' in a concurrent statement list
libghdl: :129:1: unexpected token 'constant' in a concurrent statement list
libghdl: :130:1: unexpected token 'constant' in a concurrent statement list
libghdl: :131:1: unexpected token 'constant' in a concurrent statement list
libghdl: :132:0: unexpected token 'begin' in a concurrent statement list
libghdl: :133:10: '==' is not the vhdl equality, replaced by '='
libghdl: :134:6: '==' is not the vhdl equality, replaced by '='
libghdl: :134:6: '<=' is expected instead of '='
libghdl: :134:6: unexpected token '=' in a primary
libghdl: :148:17: ':' expected after interface identifier
libghdl: :148:17: (found: an identifier)
libghdl: :148:26: ';' or ')' expected after interface
libghdl: :149:17: ':' expected after interface identifier
libghdl: :149:17: (found: an identifier)
libghdl: :149:24: ';' or ')' expected after interface
libghdl: :150:17: ':' expected after interface identifier
libghdl: :150:17: (found: an identifier)
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd] 0:00:00.220447

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd'
DOM: Error raised in libghdl.
libghdl: :30:2: object class keyword such as 'variable' is expected
libghdl: :31:2: 'begin' is expected instead of 'constant'
libghdl: :31:2: unexpected token 'constant' in a concurrent statement list
libghdl: :33:0: unexpected token 'begin' in a concurrent statement list
libghdl: :46:14: end label for an unlabeled declaration or statement

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd] 0:00:00.234595

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd'
DOM: Error raised in libghdl.
libghdl: :71:17: ':' expected after interface identifier
libghdl: :71:17: (found: an identifier)
libghdl: :71:19: interfaces must be separated by ';' (found ',')
libghdl: :72:17: ':' expected after interface identifier
libghdl: :72:17: (found: an identifier)
libghdl: :72:28: ';' or ')' expected after interface
libghdl: :83:2: object class keyword such as 'variable' is expected
libghdl: :84:2: 'begin' is expected instead of "quantity"
libghdl: :84:11: '<=' is expected instead of "w"
libghdl: :84:12: ';' expected at end of signal assignment
libghdl: :84:12: (found: an identifier)
libghdl: :84:20: '<=' is expected instead of "torq"
libghdl: :84:24: ';' expected at end of signal assignment
libghdl: :84:24: (found: an identifier)
libghdl: :84:33: '<=' is expected instead of "shaft_rotv"
libghdl: :84:43: ';' expected at end of signal assignment
libghdl: :84:43: (found: 'to')
libghdl: :84:44: unexpected token 'to' in a concurrent statement list
libghdl: :86:0: unexpected token 'begin' in a concurrent statement list
libghdl: :88:7: '==' is not the vhdl equality, replaced by '='
libghdl: :89:5: '==' is not the vhdl equality, replaced by '='
libghdl: :89:5: '<=' is expected instead of '='
libghdl: :89:5: unexpected token '=' in a primary
libghdl: :118:13: ':' expected after interface identifier
libghdl: :118:13: (found: an identifier)
libghdl: :118:16: interfaces must be separated by ';' (found ',')
libghdl: :126:2: object class keyword such as 'variable' is expected
libghdl: :128:2: 'begin' is expected instead of "quantity"
libghdl: :128:11: '<=' is expected instead of "ac_spec"
libghdl: :128:18: ';' expected at end of signal assignment
libghdl: :128:18: (found: ':')
libghdl: :128:19: unexpected token ':' in a concurrent statement list
libghdl: :130:0: unexpected token 'begin' in a concurrent statement list
libghdl: :132:55: if/use is an AMS-VHDL statement
libghdl: :133:3: '==' is not the vhdl equality, replaced by '='
libghdl: :133:3: '==' expected after expression
libghdl: :133:3: (found: '=')
libghdl: :133:3: unexpected token '=' in a primary
libghdl: :133:2: ';' is expected instead of '='
libghdl: :133:3: unexpected token '=' in a simultaneous statement list
libghdl: :135:5: '==' is not the vhdl equality, replaced by '='
libghdl: :135:5: '==' expected after expression
libghdl: :135:5: (found: '=')
libghdl: :135:5: unexpected token '=' in a primary
libghdl: :135:4: ';' is expected instead of '='
libghdl: :135:5: unexpected token '=' in a simultaneous statement list
libghdl: :159:15: ':' expected after interface identifier
libghdl: :159:15: (found: an identifier)
libghdl: :159:18: ';' or ')' expected after interface
libghdl: :161:15: ':' expected after interface identifier
libghdl: :161:15: (found: an identifier)
libghdl: :161:18: ';' or ')' expected after interface
libghdl: :171:2: object class keyword such as 'variable' is expected
libghdl: :172:2: 'begin' is expected instead of "quantity"
libghdl: :172:11: '<=' is expected instead of "r"
libghdl: :172:12: ';' expected at end of signal assignment
libghdl: :172:12: (found: ':')
libghdl: :172:14: unexpected token ':' in a concurrent statement list
libghdl: :174:0: unexpected token 'begin' in a concurrent statement list
libghdl: :186:14: end label for an unlabeled declaration or statement
libghdl: :189:4: '==' is not the vhdl equality, replaced by '='
libghdl: :189:4: '<=' is expected instead of '='
libghdl: :189:4: unexpected token '=' in a primary
libghdl: :190:4: '==' is not the vhdl equality, replaced by '='
libghdl: :190:4: '<=' is expected instead of '='
libghdl: :190:4: unexpected token '=' in a primary
libghdl: :198:2: object class keyword such as 'variable' is expected
libghdl: :199:2: 'begin' is expected instead of "quantity"
libghdl: :199:11: '<=' is expected instead of "r"
libghdl: :199:12: ';' expected at end of signal assignment
libghdl: :199:12: (found: ':')
libghdl: :199:13: unexpected token ':' in a concurrent statement list
libghdl: :200:11: '<=' is expected instead of "log10_r"
libghdl: :200:18: ';' expected at end of signal assignment
libghdl: :200:18: (found: ':')
libghdl: :200:20: unexpected token ':' in a concurrent statement list
libghdl: :202:0: unexpected token 'begin' in a concurrent statement list
libghdl: :214:14: end label for an unlabeled declaration or statement
libghdl: :217:10: '==' is not the vhdl equality, replaced by '='
libghdl: :217:10: '<=' is expected instead of '='
libghdl: :217:10: unexpected token '=' in a primary
libghdl: :218:4: '==' is not the vhdl equality, replaced by '='
libghdl: :218:4: '<=' is expected instead of '='
libghdl: :218:4: unexpected token '=' in a primary
libghdl: :219:4: '==' is not the vhdl equality, replaced by '='
libghdl: :219:4: '<=' is expected instead of '='
libghdl: :219:4: unexpected token '=' in a primary
libghdl: :277:13: ':' expected after interface identifier
libghdl: :277:13: (found: an identifier)
libghdl: :277:19: interfaces must be separated by ';' (found ',')
libghdl: :297:2: object class keyword such as 'variable' is expected
libghdl: :298:2: 'begin' is expected instead of "quantity"
libghdl: :298:11: '<=' is expected instead of "v_out"
libghdl: :298:16: ';' expected at end of signal assignment
libghdl: :298:16: (found: an identifier)
libghdl: :298:24: '<=' is expected instead of "i_out"
libghdl: :298:29: ';' expected at end of signal assignment
libghdl: :298:29: (found: an identifier)
libghdl: :298:38: '<=' is expected instead of "output"
libghdl: :300:0: unexpected token 'begin' in a concurrent statement list
libghdl: :302:8: '==' is not the vhdl equality, replaced by '='
libghdl: :303:8: '==' is not the vhdl equality, replaced by '='
libghdl: :303:8: '<=' is expected instead of '='
libghdl: :303:8: unexpected token '=' in a primary
libghdl: :327:13: ':' expected after interface identifier
libghdl: :327:13: (found: an identifier)
libghdl: :327:15: interfaces must be separated by ';' (found ',')
libghdl: :335:2: object class keyword such as 'variable' is expected
libghdl: :340:4: '==' is not the vhdl equality, replaced by '='
libghdl: :340:4: '<=' is expected instead of '='
libghdl: :340:4: unexpected token '=' in a primary
libghdl: :395:13: ':' expected after interface identifier
libghdl: :395:13: (found: an identifier)
libghdl: :395:20: ';' or ')' expected after interface
libghdl: :396:13: ':' expected after interface identifier
libghdl: :396:13: (found: an identifier)
libghdl: :396:20: ';' or ')' expected after interface
libghdl: :405:2: object class keyword such as 'variable' is expected
libghdl: :406:2: 'begin' is expected instead of "quantity"
libghdl: :406:11: '<=' is expected instead of "vref"
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd] 0:00:00.228723

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd'
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] function declaration without body
[NOT IMPLEMENTED] function declaration without body
libghdl processing time:  219.604 us
DOM translation time:    677.611 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - pwl_functions
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: pwl_functions
          File: pwl_functions.vhd
          Position: 22:8
          Declared:
      PackageBodies:
        - Name: pwl_functions
          Declared:
          - function pwl_dim1_extrap return real
          - function interpolate return real
          - function extrapolate return real
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd] 0:00:00.228792

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd'
DOM: Error raised in libghdl.
libghdl: :26:18: ':' expected after interface identifier
libghdl: :26:18: (found: an identifier)
libghdl: :26:24: ';' or ')' expected after interface
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:24: ';' or ')' expected after interface
libghdl: :34:2: object class keyword such as 'variable' is expected
libghdl: :35:2: 'begin' is expected instead of "quantity"
libghdl: :35:11: '<=' is expected instead of "vout"
libghdl: :35:15: ';' expected at end of signal assignment
libghdl: :35:15: (found: an identifier)
libghdl: :35:23: '<=' is expected instead of "iout"
libghdl: :35:27: ';' expected at end of signal assignment
libghdl: :35:27: (found: an identifier)
libghdl: :35:36: '<=' is expected instead of "output"
libghdl: :35:42: ';' expected at end of signal assignment
libghdl: :35:42: (found: 'to')
libghdl: :35:43: unexpected token 'to' in a concurrent statement list
libghdl: :36:11: '<=' is expected instead of "vin_sampled"
libghdl: :36:22: ';' expected at end of signal assignment
libghdl: :36:22: (found: ':')
libghdl: :36:23: unexpected token ':' in a concurrent statement list
libghdl: :37:11: '<=' is expected instead of "vin_zm1"
libghdl: :37:28: ';' expected at end of signal assignment
libghdl: :37:28: (found: ':')
libghdl: :37:29: unexpected token ':' in a concurrent statement list
libghdl: :38:2: unexpected token 'constant' in a concurrent statement list
libghdl: :39:2: unexpected token 'constant' in a concurrent statement list
libghdl: :40:2: unexpected token 'constant' in a concurrent statement list
libghdl: :41:2: unexpected token 'constant' in a concurrent statement list
libghdl: :42:2: unexpected token 'constant' in a concurrent statement list
libghdl: :43:2: unexpected token 'constant' in a concurrent statement list
libghdl: :45:0: unexpected token 'begin' in a concurrent statement list
libghdl: :47:15: '==' is not the vhdl equality, replaced by '='
libghdl: :49:11: '==' is not the vhdl equality, replaced by '='
libghdl: :49:11: '<=' is expected instead of '='
libghdl: :49:11: unexpected token '=' in a primary
libghdl: :51:11: '==' is not the vhdl equality, replaced by '='
libghdl: :51:11: '<=' is expected instead of '='
libghdl: :51:11: unexpected token '=' in a primary
libghdl: :53:7: '==' is not the vhdl equality, replaced by '='
libghdl: :53:7: '<=' is expected instead of '='
libghdl: :53:7: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/amp_lim.vhd] 0:00:00.231917

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/amp_lim.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:21: ';' or ')' expected after interface
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:23: interfaces must be separated by ';' (found ',')
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :32:2: 'begin' is expected instead of "quantity"
libghdl: :32:11: '<=' is expected instead of "vin"
libghdl: :32:14: ';' expected at end of signal assignment
libghdl: :32:14: (found: an identifier)
libghdl: :32:22: '<=' is expected instead of "iin"
libghdl: :32:25: ';' expected at end of signal assignment
libghdl: :32:25: (found: an identifier)
libghdl: :32:34: '<=' is expected instead of "input"
libghdl: :32:39: ';' expected at end of signal assignment
libghdl: :32:39: (found: 'to')
libghdl: :32:40: unexpected token 'to' in a concurrent statement list
libghdl: :33:11: '<=' is expected instead of "vout"
libghdl: :33:15: ';' expected at end of signal assignment
libghdl: :33:15: (found: an identifier)
libghdl: :33:23: '<=' is expected instead of "iout"
libghdl: :33:27: ';' expected at end of signal assignment
libghdl: :33:27: (found: an identifier)
libghdl: :33:36: '<=' is expected instead of "output"
libghdl: :33:42: ';' expected at end of signal assignment
libghdl: :33:42: (found: 'to')
libghdl: :33:43: unexpected token 'to' in a concurrent statement list
libghdl: :34:11: '<=' is expected instead of "v_amplified"
libghdl: :34:22: ';' expected at end of signal assignment
libghdl: :34:22: (found: ':')
libghdl: :34:23: unexpected token ':' in a concurrent statement list
libghdl: :35:2: unexpected token 'constant' in a concurrent statement list
libghdl: :37:0: unexpected token 'begin' in a concurrent statement list
libghdl: :39:14: '==' is not the vhdl equality, replaced by '='
libghdl: :41:30: if/use is an AMS-VHDL statement
libghdl: :42:9: '==' is not the vhdl equality, replaced by '='
libghdl: :42:9: '==' expected after expression
libghdl: :42:9: (found: '=')
libghdl: :42:9: unexpected token '=' in a primary
libghdl: :42:8: ';' is expected instead of '='
libghdl: :42:9: unexpected token '=' in a simultaneous statement list
libghdl: :44:9: '==' is not the vhdl equality, replaced by '='
libghdl: :44:9: '==' expected after expression
libghdl: :44:9: (found: '=')
libghdl: :44:9: unexpected token '=' in a primary
libghdl: :44:8: ';' is expected instead of '='
libghdl: :44:9: unexpected token '=' in a simultaneous statement list
libghdl: :47:8: '<=' is expected instead of 'on'
libghdl: :47:8: unexpected token 'on' in a primary
libghdl: :47:7: ';' expected at end of signal assignment
libghdl: :47:7: (found: 'on')
libghdl: :47:8: unexpected token 'on' in a concurrent statement list
libghdl: :50:8: '==' is not the vhdl equality, replaced by '='
libghdl: :50:8: '<=' is expected instead of '='
libghdl: :50:8: unexpected token '=' in a primary
libghdl: :51:6: '==' is not the vhdl equality, replaced by '='
libghdl: :51:6: '<=' is expected instead of '='
libghdl: :51:6: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd] 0:00:00.231401

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:24: interfaces must be separated by ';' (found ',')
libghdl: :36:2: object class keyword such as 'variable' is expected
libghdl: :37:2: 'begin' is expected instead of "quantity"
libghdl: :37:11: '<=' is expected instead of "v_out"
libghdl: :37:16: ';' expected at end of signal assignment
libghdl: :37:16: (found: an identifier)
libghdl: :37:24: '<=' is expected instead of "i_out"
libghdl: :37:29: ';' expected at end of signal assignment
libghdl: :37:29: (found: an identifier)
libghdl: :37:38: '<=' is expected instead of "output"
libghdl: :39:0: unexpected token 'begin' in a concurrent statement list
libghdl: :41:7: '==' is not the vhdl equality, replaced by '='
libghdl: :57:2: object class keyword such as 'variable' is expected
libghdl: :58:2: 'begin' is expected instead of "quantity"
libghdl: :58:11: '<=' is expected instead of "v_out"
libghdl: :58:16: ';' expected at end of signal assignment
libghdl: :58:16: (found: an identifier)
libghdl: :58:24: '<=' is expected instead of "i_out"
libghdl: :58:29: ';' expected at end of signal assignment
libghdl: :58:29: (found: an identifier)
libghdl: :58:38: '<=' is expected instead of "output"
libghdl: :60:0: unexpected token 'begin' in a concurrent statement list
libghdl: :62:8: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd] 0:00:00.248308

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd'
DOM: Error raised in libghdl.
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:21: interfaces must be separated by ';' (found ',')
libghdl: :28:12: ':' expected after interface identifier
libghdl: :28:12: (found: an identifier)
libghdl: :28:18: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "vin2"
libghdl: :33:15: ';' expected at end of signal assignment
libghdl: :33:15: (found: an identifier)
libghdl: :33:23: '<=' is expected instead of "in2"
libghdl: :33:26: ';' expected at end of signal assignment
libghdl: :33:26: (found: 'to')
libghdl: :33:27: unexpected token 'to' in a concurrent statement list
libghdl: :34:11: '<=' is expected instead of "vout"
libghdl: :34:15: ';' expected at end of signal assignment
libghdl: :34:15: (found: an identifier)
libghdl: :34:23: '<=' is expected instead of "iout"
libghdl: :34:27: ';' expected at end of signal assignment
libghdl: :34:27: (found: an identifier)
libghdl: :34:36: '<=' is expected instead of "output"
libghdl: :34:42: ';' expected at end of signal assignment
libghdl: :34:42: (found: 'to')
libghdl: :34:43: unexpected token 'to' in a concurrent statement list
libghdl: :36:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:6: '==' is not the vhdl equality, replaced by '='
libghdl: :50:18: ':' expected after interface identifier
libghdl: :50:18: (found: an identifier)
libghdl: :50:24: ';' or ')' expected after interface
libghdl: :51:12: ':' expected after interface identifier
libghdl: :51:12: (found: an identifier)
libghdl: :51:18: ';' or ')' expected after interface
libghdl: :56:2: object class keyword such as 'variable' is expected
libghdl: :57:2: 'begin' is expected instead of "quantity"
libghdl: :57:11: '<=' is expected instead of "vout"
libghdl: :57:15: ';' expected at end of signal assignment
libghdl: :57:15: (found: an identifier)
libghdl: :57:23: '<=' is expected instead of "iout"
libghdl: :57:27: ';' expected at end of signal assignment
libghdl: :57:27: (found: an identifier)
libghdl: :57:36: '<=' is expected instead of "output"
libghdl: :57:42: ';' expected at end of signal assignment
libghdl: :57:42: (found: 'to')
libghdl: :57:43: unexpected token 'to' in a concurrent statement list
libghdl: :59:0: unexpected token 'begin' in a concurrent statement list
libghdl: :60:6: '==' is not the vhdl equality, replaced by '='
libghdl: :75:11: ':' expected after interface identifier
libghdl: :75:11: (found: an identifier)
libghdl: :75:16: ';' or ')' expected after interface
libghdl: :76:11: ':' expected after interface identifier
libghdl: :76:11: (found: an identifier)
libghdl: :76:17: ';' or ')' expected after interface
libghdl: :80:3: object class keyword such as 'variable' is expected
libghdl: :81:3: 'begin' is expected instead of "quantity"
libghdl: :81:12: '<=' is expected instead of "vout"
libghdl: :81:16: ';' expected at end of signal assignment
libghdl: :81:16: (found: an identifier)
libghdl: :81:24: '<=' is expected instead of "iout"
libghdl: :81:28: ';' expected at end of signal assignment
libghdl: :81:28: (found: an identifier)
libghdl: :81:37: '<=' is expected instead of "output"
libghdl: :81:43: ';' expected at end of signal assignment
libghdl: :81:43: (found: 'to')
libghdl: :81:44: unexpected token 'to' in a concurrent statement list
libghdl: :82:1: unexpected token 'constant' in a concurrent statement list
libghdl: :83:0: unexpected token 'begin' in a concurrent statement list
libghdl: :84:21: if/use is an AMS-VHDL statement
libghdl: :85:7: '==' is not the vhdl equality, replaced by '='
libghdl: :85:7: '==' expected after expression
libghdl: :85:7: (found: '=')
libghdl: :85:7: unexpected token '=' in a primary
libghdl: :85:6: ';' is expected instead of '='
libghdl: :85:7: unexpected token '=' in a simultaneous statement list
libghdl: :87:7: '==' is not the vhdl equality, replaced by '='
libghdl: :87:7: '==' expected after expression
libghdl: :87:7: (found: '=')
libghdl: :87:7: unexpected token '=' in a primary
libghdl: :87:6: ';' is expected instead of '='
libghdl: :87:7: unexpected token '=' in a simultaneous statement list
libghdl: :89:7: '==' is not the vhdl equality, replaced by '='
libghdl: :89:7: '==' expected after expression
libghdl: :89:7: (found: '=')
libghdl: :89:7: unexpected token '=' in a primary
libghdl: :89:6: ';' is expected instead of '='
libghdl: :89:7: unexpected token '=' in a simultaneous statement list
libghdl: :91:7: '<=' is expected instead of 'on'
libghdl: :91:7: unexpected token 'on' in a primary
libghdl: :91:6: ';' expected at end of signal assignment
libghdl: :91:6: (found: 'on')
libghdl: :91:7: unexpected token 'on' in a concurrent statement list
libghdl: :119:18: ':' expected after interface identifier
libghdl: :119:18: (found: an identifier)
libghdl: :119:23: ';' or ')' expected after interface
libghdl: :120:12: ':' expected after interface identifier
libghdl: :120:12: (found: an identifier)
libghdl: :120:18: ';' or ')' expected after interface
libghdl: :124:2: object class keyword such as 'variable' is expected
libghdl: :125:2: 'begin' is expected instead of "quantity"
libghdl: :125:11: '<=' is expected instead of "vout"
libghdl: :125:15: ';' expected at end of signal assignment
libghdl: :125:15: (found: an identifier)
libghdl: :125:23: '<=' is expected instead of "iout"
libghdl: :125:27: ';' expected at end of signal assignment
libghdl: :125:27: (found: an identifier)
libghdl: :125:36: '<=' is expected instead of "output"
libghdl: :125:42: ';' expected at end of signal assignment
libghdl: :125:42: (found: 'to')
libghdl: :125:43: unexpected token 'to' in a concurrent statement list
libghdl: :127:10: '<=' is expected instead of "vin_temp"
libghdl: :127:18: ';' expected at end of signal assignment
libghdl: :127:18: (found: ':')
libghdl: :127:19: unexpected token ':' in a concurrent statement list
libghdl: :128:1: unexpected token 'constant' in a concurrent statement list
libghdl: :129:1: unexpected token 'constant' in a concurrent statement list
libghdl: :130:1: unexpected token 'constant' in a concurrent statement list
libghdl: :131:1: unexpected token 'constant' in a concurrent statement list
libghdl: :132:0: unexpected token 'begin' in a concurrent statement list
libghdl: :133:10: '==' is not the vhdl equality, replaced by '='
libghdl: :134:6: '==' is not the vhdl equality, replaced by '='
libghdl: :134:6: '<=' is expected instead of '='
libghdl: :134:6: unexpected token '=' in a primary
libghdl: :147:17: ':' expected after interface identifier
libghdl: :147:17: (found: an identifier)
libghdl: :147:26: ';' or ')' expected after interface
libghdl: :148:17: ':' expected after interface identifier
libghdl: :148:17: (found: an identifier)
libghdl: :148:24: ';' or ')' expected after interface
libghdl: :149:17: ':' expected after interface identifier
libghdl: :149:17: (found: an identifier)
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd] 0:00:00.223670

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd'
DOM: Error raised in libghdl.
libghdl: :31:4: object class keyword such as 'variable' is expected
libghdl: :32:4: 'begin' is expected instead of "terminal"
libghdl: :32:13: '<=' is expected instead of "out_dot"
libghdl: :32:57: ';' expected at end of signal assignment
libghdl: :32:57: (found: ':')
libghdl: :32:58: unexpected token ':' in a concurrent statement list
libghdl: :33:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/prop_pwl.vhd] 0:00:00.222641

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/prop_pwl.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:25: ';' or ')' expected after interface
libghdl: :34:2: object class keyword such as 'variable' is expected
libghdl: :38:7: '==' is not the vhdl equality, replaced by '='
libghdl: :38:7: '<=' is expected instead of '='
libghdl: :38:7: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd] 0:00:00.226339

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd'
DOM: Error raised in libghdl.
libghdl: :29:4: object class keyword such as 'variable' is expected
libghdl: :30:4: 'begin' is expected instead of "terminal"
libghdl: :30:13: '<=' is expected instead of "out_opamp1"
libghdl: :30:61: ';' expected at end of signal assignment
libghdl: :30:61: (found: ':')
libghdl: :30:62: unexpected token ':' in a concurrent statement list
libghdl: :31:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd] 0:00:00.232156

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd'
DOM: Error raised in libghdl.
libghdl: :31:4: object class keyword such as 'variable' is expected
libghdl: :32:4: 'begin' is expected instead of "terminal"
libghdl: :32:13: '<=' is expected instead of "out_dot"
libghdl: :32:77: ';' expected at end of signal assignment
libghdl: :32:77: (found: ':')
libghdl: :32:78: unexpected token ':' in a concurrent statement list
libghdl: :33:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd] 0:00:00.235332

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd'
DOM: Error raised in libghdl.
libghdl: :41:2: object class keyword such as 'variable' is expected
libghdl: :45:2: 'begin' is expected instead of 'function'
libghdl: :45:2: unexpected token 'function' in a concurrent statement list
libghdl: :49:11: '<=' is expected instead of "source1"
libghdl: :49:18: ';' expected at end of signal assignment
libghdl: :49:18: (found: ':')
libghdl: :49:19: unexpected token ':' in a concurrent statement list
libghdl: :53:11: '<=' is expected instead of "source2"
libghdl: :53:18: ';' expected at end of signal assignment
libghdl: :53:18: (found: ':')
libghdl: :53:19: unexpected token ':' in a concurrent statement list
libghdl: :57:2: unexpected token 'function' in a concurrent statement list
libghdl: :60:5: missing ";" at end of architecture
libghdl: :62:0: missing entity, architecture, package or configuration

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd] 0:00:00.241170

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd'
DOM: Error raised in libghdl.
libghdl: :33:4: object class keyword such as 'variable' is expected
libghdl: :34:4: 'begin' is expected instead of "terminal"
libghdl: :34:13: '<=' is expected instead of "g"
libghdl: :34:14: ';' expected at end of signal assignment
libghdl: :34:14: (found: ':')
libghdl: :34:15: unexpected token ':' in a concurrent statement list
libghdl: :35:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd] 0:00:00.245618

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:25: interfaces must be separated by ';' (found ',')
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :32:2: 'begin' is expected instead of "quantity"
libghdl: :32:11: '<=' is expected instead of "v_out"
libghdl: :32:16: ';' expected at end of signal assignment
libghdl: :32:16: (found: an identifier)
libghdl: :32:24: '<=' is expected instead of "i_out"
libghdl: :32:29: ';' expected at end of signal assignment
libghdl: :32:29: (found: an identifier)
libghdl: :32:38: '<=' is expected instead of "output"
libghdl: :33:11: '<=' is expected instead of "v_amplified"
libghdl: :33:22: ';' expected at end of signal assignment
libghdl: :33:22: (found: ':')
libghdl: :33:23: unexpected token ':' in a concurrent statement list
libghdl: :35:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:14: '==' is not the vhdl equality, replaced by '='
libghdl: :39:8: '==' is not the vhdl equality, replaced by '='
libghdl: :39:8: '<=' is expected instead of '='
libghdl: :39:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd] 0:00:00.236915

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:22: interfaces must be separated by ';' (found ',')
libghdl: :30:2: object class keyword such as 'variable' is expected
libghdl: :31:2: 'begin' is expected instead of "quantity"
libghdl: :31:11: '<=' is expected instead of "vds"
libghdl: :31:14: ';' expected at end of signal assignment
libghdl: :31:14: (found: an identifier)
libghdl: :31:22: '<=' is expected instead of "ids"
libghdl: :31:25: ';' expected at end of signal assignment
libghdl: :31:25: (found: an identifier)
libghdl: :31:34: '<=' is expected instead of "drain"
libghdl: :31:39: ';' expected at end of signal assignment
libghdl: :31:39: (found: 'to')
libghdl: :31:40: unexpected token 'to' in a concurrent statement list
libghdl: :32:11: '<=' is expected instead of "vsd"
libghdl: :32:14: ';' expected at end of signal assignment
libghdl: :32:14: (found: an identifier)
libghdl: :32:22: '<=' is expected instead of "source"
libghdl: :32:28: ';' expected at end of signal assignment
libghdl: :32:28: (found: 'to')
libghdl: :32:29: unexpected token 'to' in a concurrent statement list
libghdl: :33:11: '<=' is expected instead of "vgd"
libghdl: :33:14: ';' expected at end of signal assignment
libghdl: :33:14: (found: an identifier)
libghdl: :33:22: '<=' is expected instead of "igd"
libghdl: :33:25: ';' expected at end of signal assignment
libghdl: :33:25: (found: an identifier)
libghdl: :33:34: '<=' is expected instead of "gate"
libghdl: :33:38: ';' expected at end of signal assignment
libghdl: :33:38: (found: 'to')
libghdl: :33:39: unexpected token 'to' in a concurrent statement list
libghdl: :34:2: unexpected token 'constant' in a concurrent statement list
libghdl: :35:2: unexpected token 'constant' in a concurrent statement list
libghdl: :38:0: unexpected token 'begin' in a concurrent statement list
libghdl: :40:16: if/use is an AMS-VHDL statement
libghdl: :42:10: '==' is not the vhdl equality, replaced by '='
libghdl: :42:10: '==' expected after expression
libghdl: :42:10: (found: '=')
libghdl: :42:10: unexpected token '=' in a primary
libghdl: :42:9: ';' is expected instead of '='
libghdl: :42:10: unexpected token '=' in a simultaneous statement list
libghdl: :44:10: '==' is not the vhdl equality, replaced by '='
libghdl: :44:10: '==' expected after expression
libghdl: :44:10: (found: '=')
libghdl: :44:10: unexpected token '=' in a primary
libghdl: :44:9: ';' is expected instead of '='
libghdl: :44:10: unexpected token '=' in a simultaneous statement list
libghdl: :46:10: '==' is not the vhdl equality, replaced by '='
libghdl: :46:10: '==' expected after expression
libghdl: :46:10: (found: '=')
libghdl: :46:10: unexpected token '=' in a primary
libghdl: :46:9: ';' is expected instead of '='
libghdl: :46:10: unexpected token '=' in a simultaneous statement list
libghdl: :50:10: '==' is not the vhdl equality, replaced by '='
libghdl: :50:10: '==' expected after expression
libghdl: :50:10: (found: '=')
libghdl: :50:10: unexpected token '=' in a primary
libghdl: :50:9: ';' is expected instead of '='
libghdl: :50:10: unexpected token '=' in a simultaneous statement list
libghdl: :52:10: '==' is not the vhdl equality, replaced by '='
libghdl: :52:10: '==' expected after expression
libghdl: :52:10: (found: '=')
libghdl: :52:10: unexpected token '=' in a primary
libghdl: :52:9: ';' is expected instead of '='
libghdl: :52:10: unexpected token '=' in a simultaneous statement list
libghdl: :54:10: '==' is not the vhdl equality, replaced by '='
libghdl: :54:10: '==' expected after expression
libghdl: :54:10: (found: '=')
libghdl: :54:10: unexpected token '=' in a primary
libghdl: :54:9: ';' is expected instead of '='
libghdl: :54:10: unexpected token '=' in a simultaneous statement list
libghdl: :58:6: '==' is not the vhdl equality, replaced by '='
libghdl: :58:6: '<=' is expected instead of '='
libghdl: :58:6: unexpected token '=' in a primary
libghdl: :59:6: '==' is not the vhdl equality, replaced by '='
libghdl: :59:6: '<=' is expected instead of '='
libghdl: :59:6: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd] 0:00:00.243954

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd'
DOM: Error raised in libghdl.
libghdl: :29:4: object class keyword such as 'variable' is expected
libghdl: :30:4: 'begin' is expected instead of "terminal"
libghdl: :30:13: '<=' is expected instead of "out_opamp1"
libghdl: :30:82: ';' expected at end of signal assignment
libghdl: :30:82: (found: ':')
libghdl: :30:83: unexpected token ':' in a concurrent statement list
libghdl: :31:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd] 0:00:00.225136

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd'
DOM: Error raised in libghdl.
libghdl: :26:18: ':' expected after interface identifier
libghdl: :26:18: (found: an identifier)
libghdl: :26:20: interfaces must be separated by ';' (found ',')
libghdl: :30:2: object class keyword such as 'variable' is expected
libghdl: :32:4: '==' is not the vhdl equality, replaced by '='
libghdl: :32:4: '<=' is expected instead of '='
libghdl: :32:4: unexpected token '=' in a primary
libghdl: :40:18: ':' expected after interface identifier
libghdl: :40:18: (found: an identifier)
libghdl: :40:20: interfaces must be separated by ';' (found ',')
libghdl: :44:2: object class keyword such as 'variable' is expected
libghdl: :46:4: '==' is not the vhdl equality, replaced by '='
libghdl: :46:4: '<=' is expected instead of '='
libghdl: :46:4: unexpected token '=' in a primary
libghdl: :55:18: ':' expected after interface identifier
libghdl: :55:18: (found: an identifier)
libghdl: :55:24: ';' or ')' expected after interface
libghdl: :56:18: ':' expected after interface identifier
libghdl: :56:18: (found: an identifier)
libghdl: :56:25: ';' or ')' expected after interface

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd] 0:00:00.223611

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd'
DOM: Error raised in libghdl.
libghdl: :28:4: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd] 0:00:00.225655

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:24: ';' or ')' expected after interface
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:25: ';' or ')' expected after interface
libghdl: :31:2: object class keyword such as 'variable' is expected
libghdl: :32:2: 'begin' is expected instead of "quantity"
libghdl: :32:11: '<=' is expected instead of "vout"
libghdl: :32:15: ';' expected at end of signal assignment
libghdl: :32:15: (found: an identifier)
libghdl: :32:23: '<=' is expected instead of "iout"
libghdl: :32:27: ';' expected at end of signal assignment
libghdl: :32:27: (found: an identifier)
libghdl: :32:36: '<=' is expected instead of "output"
libghdl: :32:42: ';' expected at end of signal assignment
libghdl: :32:42: (found: 'to')
libghdl: :32:43: unexpected token 'to' in a concurrent statement list
libghdl: :33:2: unexpected token 'constant' in a concurrent statement list
libghdl: :35:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:6: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd] 0:00:00.233333

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd'
DOM: Error raised in libghdl.
libghdl: :26:18: ':' expected after interface identifier
libghdl: :26:18: (found: an identifier)
libghdl: :26:23: ';' or ')' expected after interface
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:24: ';' or ')' expected after interface
libghdl: :34:2: object class keyword such as 'variable' is expected
libghdl: :35:2: 'begin' is expected instead of "quantity"
libghdl: :35:11: '<=' is expected instead of "vout"
libghdl: :35:15: ';' expected at end of signal assignment
libghdl: :35:15: (found: an identifier)
libghdl: :35:23: '<=' is expected instead of "iout"
libghdl: :35:27: ';' expected at end of signal assignment
libghdl: :35:27: (found: an identifier)
libghdl: :35:36: '<=' is expected instead of "output"
libghdl: :35:42: ';' expected at end of signal assignment
libghdl: :35:42: (found: 'to')
libghdl: :35:43: unexpected token 'to' in a concurrent statement list
libghdl: :36:2: unexpected token 'constant' in a concurrent statement list
libghdl: :37:2: unexpected token 'constant' in a concurrent statement list
libghdl: :38:2: unexpected token 'constant' in a concurrent statement list
libghdl: :39:2: unexpected token 'constant' in a concurrent statement list
libghdl: :40:2: unexpected token 'constant' in a concurrent statement list
libghdl: :41:2: unexpected token 'constant' in a concurrent statement list
libghdl: :42:2: unexpected token 'constant' in a concurrent statement list
libghdl: :43:2: unexpected token 'constant' in a concurrent statement list
libghdl: :45:0: unexpected token 'begin' in a concurrent statement list
libghdl: :47:7: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd] 0:00:00.234354

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd'
DOM: Error raised in libghdl.
libghdl: :29:18: ':' expected after interface identifier
libghdl: :29:18: (found: an identifier)
libghdl: :29:21: interfaces must be separated by ';' (found ',')
libghdl: :45:2: object class keyword such as 'variable' is expected
libghdl: :47:2: 'begin' is expected instead of "quantity"
libghdl: :47:11: '<=' is expected instead of "ac_spec"
libghdl: :47:18: ';' expected at end of signal assignment
libghdl: :47:18: (found: ':')
libghdl: :47:19: unexpected token ':' in a concurrent statement list
libghdl: :50:0: unexpected token 'begin' in a concurrent statement list
libghdl: :52:55: if/use is an AMS-VHDL statement
libghdl: :53:9: '==' is not the vhdl equality, replaced by '='
libghdl: :53:9: '==' expected after expression
libghdl: :53:9: (found: '=')
libghdl: :53:9: unexpected token '=' in a primary
libghdl: :53:8: ';' is expected instead of '='
libghdl: :53:9: unexpected token '=' in a simultaneous statement list
libghdl: :55:9: '==' is not the vhdl equality, replaced by '='
libghdl: :55:9: '==' expected after expression
libghdl: :55:9: (found: '=')
libghdl: :55:9: unexpected token '=' in a primary
libghdl: :55:8: ';' is expected instead of '='
libghdl: :55:9: unexpected token '=' in a simultaneous statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd] 0:00:00.249680

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd'
DOM: Error raised in libghdl.
libghdl: :29:18: ':' expected after interface identifier
libghdl: :29:18: (found: an identifier)
libghdl: :29:24: interfaces must be separated by ';' (found ',')
libghdl: :40:2: object class keyword such as 'variable' is expected
libghdl: :41:2: 'begin' is expected instead of "quantity"
libghdl: :41:11: '<=' is expected instead of "v_out"
libghdl: :41:16: ';' expected at end of signal assignment
libghdl: :41:16: (found: an identifier)
libghdl: :41:24: '<=' is expected instead of "i_out"
libghdl: :41:29: ';' expected at end of signal assignment
libghdl: :41:29: (found: an identifier)
libghdl: :41:38: '<=' is expected instead of "output"
libghdl: :43:0: unexpected token 'begin' in a concurrent statement list
libghdl: :45:8: '==' is not the vhdl equality, replaced by '='
libghdl: :47:8: '==' is not the vhdl equality, replaced by '='
libghdl: :47:8: '<=' is expected instead of '='
libghdl: :47:8: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd] 0:00:00.237126

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd'
DOM: Error raised in libghdl.
libghdl: :35:2: object class keyword such as 'variable' is expected
libghdl: :36:2: 'begin' is expected instead of "quantity"
libghdl: :36:11: '<=' is expected instead of "resistor_voltage"
libghdl: :36:27: ';' expected at end of signal assignment
libghdl: :36:27: (found: an identifier)
libghdl: :36:35: '<=' is expected instead of "resistor_current"
libghdl: :36:51: ';' expected at end of signal assignment
libghdl: :36:51: (found: an identifier)
libghdl: :36:60: '<=' is expected instead of "r_p1"
libghdl: :36:64: ';' expected at end of signal assignment
libghdl: :36:64: (found: 'to')
libghdl: :36:65: unexpected token 'to' in a concurrent statement list
libghdl: :38:2: unexpected token 'constant' in a concurrent statement list
libghdl: :40:2: unexpected token 'function' in a concurrent statement list
libghdl: :43:5: missing ";" at end of architecture
libghdl: :45:2: missing entity, architecture, package or configuration
libghdl: :46:2: missing entity, architecture, package or configuration
libghdl: :47:2: missing entity, architecture, package or configuration
libghdl: :51:2: missing entity, architecture, package or configuration
libghdl: :55:2: missing entity, architecture, package or configuration
libghdl: :59:2: missing entity, architecture, package or configuration
libghdl: :63:0: missing entity, architecture, package or configuration
libghdl: :67:19: '==' is not the vhdl equality, replaced by '='
libghdl: :71:0: missing entity, architecture, package or configuration

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd] 0:00:00.232484

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:24: ';' or ')' expected after interface
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:25: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "vout"
libghdl: :33:15: ';' expected at end of signal assignment
libghdl: :33:15: (found: an identifier)
libghdl: :33:23: '<=' is expected instead of "iout"
libghdl: :33:27: ';' expected at end of signal assignment
libghdl: :33:27: (found: an identifier)
libghdl: :33:36: '<=' is expected instead of "output"
libghdl: :33:42: ';' expected at end of signal assignment
libghdl: :33:42: (found: 'to')
libghdl: :33:43: unexpected token 'to' in a concurrent statement list
libghdl: :34:2: unexpected token 'constant' in a concurrent statement list
libghdl: :35:2: unexpected token 'constant' in a concurrent statement list
libghdl: :36:2: unexpected token 'constant' in a concurrent statement list
libghdl: :38:0: unexpected token 'begin' in a concurrent statement list
libghdl: :40:7: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd] 0:00:00.230063

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd'
DOM: Error raised in libghdl.
libghdl: :26:18: ':' expected after interface identifier
libghdl: :26:18: (found: an identifier)
libghdl: :26:20: interfaces must be separated by ';' (found ',')
libghdl: :30:2: object class keyword such as 'variable' is expected
libghdl: :32:4: '==' is not the vhdl equality, replaced by '='
libghdl: :32:4: '<=' is expected instead of '='
libghdl: :32:4: unexpected token '=' in a primary
libghdl: :40:18: ':' expected after interface identifier
libghdl: :40:18: (found: an identifier)
libghdl: :40:20: interfaces must be separated by ';' (found ',')
libghdl: :44:2: object class keyword such as 'variable' is expected
libghdl: :46:4: '==' is not the vhdl equality, replaced by '='
libghdl: :46:4: '<=' is expected instead of '='
libghdl: :46:4: unexpected token '=' in a primary
libghdl: :59:18: ':' expected after interface identifier
libghdl: :59:18: (found: an identifier)
libghdl: :59:23: ';' or ')' expected after interface
libghdl: :60:18: ':' expected after interface identifier
libghdl: :60:18: (found: an identifier)
libghdl: :60:24: ';' or ')' expected after interface
libghdl: :91:2: object class keyword such as 'variable' is expected
libghdl: :92:2: 'begin' is expected instead of "quantity"
libghdl: :92:11: '<=' is expected instead of "vout"
libghdl: :92:15: ';' expected at end of signal assignment
libghdl: :92:15: (found: an identifier)
libghdl: :92:23: '<=' is expected instead of "iout"
libghdl: :92:27: ';' expected at end of signal assignment
libghdl: :92:27: (found: an identifier)
libghdl: :92:36: '<=' is expected instead of "output"
libghdl: :92:42: ';' expected at end of signal assignment
libghdl: :92:42: (found: 'to')
libghdl: :92:43: unexpected token 'to' in a concurrent statement list
libghdl: :93:2: unexpected token 'constant' in a concurrent statement list
libghdl: :94:2: unexpected token 'constant' in a concurrent statement list
libghdl: :96:0: unexpected token 'begin' in a concurrent statement list
libghdl: :101:6: '==' is not the vhdl equality, replaced by '='
libghdl: :101:6: '<=' is expected instead of '='
libghdl: :101:6: unexpected token '=' in a primary
libghdl: :109:2: object class keyword such as 'variable' is expected
libghdl: :110:2: 'begin' is expected instead of "quantity"
libghdl: :110:11: '<=' is expected instead of "vout"
libghdl: :110:15: ';' expected at end of signal assignment
libghdl: :110:15: (found: an identifier)
libghdl: :110:23: '<=' is expected instead of "iout"
libghdl: :110:27: ';' expected at end of signal assignment
libghdl: :110:27: (found: an identifier)
libghdl: :110:36: '<=' is expected instead of "output"
libghdl: :110:42: ';' expected at end of signal assignment
libghdl: :110:42: (found: 'to')
libghdl: :110:43: unexpected token 'to' in a concurrent statement list
libghdl: :111:2: unexpected token 'constant' in a concurrent statement list
libghdl: :112:2: unexpected token 'constant' in a concurrent statement list
libghdl: :113:2: unexpected token 'constant' in a concurrent statement list
libghdl: :115:0: unexpected token 'begin' in a concurrent statement list
libghdl: :120:7: '==' is not the vhdl equality, replaced by '='
libghdl: :120:7: '<=' is expected instead of '='
libghdl: :120:7: unexpected token '=' in a primary
libghdl: :128:2: object class keyword such as 'variable' is expected
libghdl: :129:2: 'begin' is expected instead of "quantity"
libghdl: :129:11: '<=' is expected instead of "vout"
libghdl: :129:15: ';' expected at end of signal assignment
libghdl: :129:15: (found: an identifier)
libghdl: :129:23: '<=' is expected instead of "iout"
libghdl: :129:27: ';' expected at end of signal assignment
libghdl: :129:27: (found: an identifier)
libghdl: :129:36: '<=' is expected instead of "output"
libghdl: :129:42: ';' expected at end of signal assignment
libghdl: :129:42: (found: 'to')
libghdl: :129:43: unexpected token 'to' in a concurrent statement list
libghdl: :130:11: '<=' is expected instead of "vin_sampled"
libghdl: :130:22: ';' expected at end of signal assignment
libghdl: :130:22: (found: ':')
libghdl: :130:23: unexpected token ':' in a concurrent statement list
libghdl: :131:11: '<=' is expected instead of "vin_zm1"
libghdl: :131:28: ';' expected at end of signal assignment
libghdl: :131:28: (found: ':')
libghdl: :131:29: unexpected token ':' in a concurrent statement list
libghdl: :132:2: unexpected token 'constant' in a concurrent statement list
libghdl: :133:2: unexpected token 'constant' in a concurrent statement list
libghdl: :134:2: unexpected token 'constant' in a concurrent statement list
libghdl: :135:2: unexpected token 'constant' in a concurrent statement list
libghdl: :136:2: unexpected token 'constant' in a concurrent statement list
libghdl: :137:2: unexpected token 'constant' in a concurrent statement list
libghdl: :139:0: unexpected token 'begin' in a concurrent statement list
libghdl: :141:15: '==' is not the vhdl equality, replaced by '='
libghdl: :143:11: '==' is not the vhdl equality, replaced by '='
libghdl: :143:11: '<=' is expected instead of '='
libghdl: :143:11: unexpected token '=' in a primary
libghdl: :145:11: '==' is not the vhdl equality, replaced by '='
libghdl: :145:11: '<=' is expected instead of '='
libghdl: :145:11: unexpected token '=' in a primary
libghdl: :147:7: '==' is not the vhdl equality, replaced by '='
libghdl: :147:7: '<=' is expected instead of '='
libghdl: :147:7: unexpected token '=' in a primary
libghdl: :155:2: object class keyword such as 'variable' is expected
libghdl: :156:2: 'begin' is expected instead of "quantity"
libghdl: :156:11: '<=' is expected instead of "vout"
libghdl: :156:15: ';' expected at end of signal assignment
libghdl: :156:15: (found: an identifier)
libghdl: :156:23: '<=' is expected instead of "iout"
libghdl: :156:27: ';' expected at end of signal assignment
libghdl: :156:27: (found: an identifier)
libghdl: :156:36: '<=' is expected instead of "output"
libghdl: :156:42: ';' expected at end of signal assignment
libghdl: :156:42: (found: 'to')
libghdl: :156:43: unexpected token 'to' in a concurrent statement list
libghdl: :157:2: unexpected token 'constant' in a concurrent statement list
libghdl: :158:2: unexpected token 'constant' in a concurrent statement list
libghdl: :159:2: unexpected token 'constant' in a concurrent statement list
libghdl: :160:2: unexpected token 'constant' in a concurrent statement list
libghdl: :161:2: unexpected token 'constant' in a concurrent statement list
libghdl: :162:2: unexpected token 'constant' in a concurrent statement list
libghdl: :163:2: unexpected token 'constant' in a concurrent statement list
libghdl: :164:2: unexpected token 'constant' in a concurrent statement list
libghdl: :166:0: unexpected token 'begin' in a concurrent statement list
libghdl: :168:7: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/resistor.vhd] 0:00:00.235330

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/resistor.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:20: interfaces must be separated by ';' (found ',')
libghdl: :27:2: object class keyword such as 'variable' is expected
libghdl: :28:2: 'begin' is expected instead of 'constant'
libghdl: :28:2: unexpected token 'constant' in a concurrent statement list
libghdl: :29:0: unexpected token 'begin' in a concurrent statement list
libghdl: :30:4: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd] 0:00:00.251041

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd'
DOM: Error raised in libghdl.
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:21: interfaces must be separated by ';' (found ',')
libghdl: :34:2: object class keyword such as 'variable' is expected
libghdl: :36:2: 'begin' is expected instead of "quantity"
libghdl: :36:11: '<=' is expected instead of "ac_spec"
libghdl: :36:18: ';' expected at end of signal assignment
libghdl: :36:18: (found: ':')
libghdl: :36:19: unexpected token ':' in a concurrent statement list
libghdl: :38:0: unexpected token 'begin' in a concurrent statement list
libghdl: :40:55: if/use is an AMS-VHDL statement
libghdl: :41:9: '==' is not the vhdl equality, replaced by '='
libghdl: :41:9: '==' expected after expression
libghdl: :41:9: (found: '=')
libghdl: :41:9: unexpected token '=' in a primary
libghdl: :41:8: ';' is expected instead of '='
libghdl: :41:9: unexpected token '=' in a simultaneous statement list
libghdl: :43:9: '==' is not the vhdl equality, replaced by '='
libghdl: :43:9: '==' expected after expression
libghdl: :43:9: (found: '=')
libghdl: :43:9: unexpected token '=' in a primary
libghdl: :43:8: ';' is expected instead of '='
libghdl: :43:9: unexpected token '=' in a simultaneous statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_pulse.vhd] 0:00:00.257191

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_pulse.vhd'
DOM: Error raised in libghdl.
libghdl: :31:29: space is required between number and unit name
libghdl: :37:18: ':' expected after interface identifier
libghdl: :37:18: (found: an identifier)
libghdl: :37:25: ';' or ')' expected after interface
libghdl: :45:2: object class keyword such as 'variable' is expected
libghdl: :48:2: 'begin' is expected instead of 'signal'
libghdl: :48:2: unexpected token 'signal' in a concurrent statement list
libghdl: :49:2: unexpected token 'constant' in a concurrent statement list
libghdl: :51:0: unexpected token 'begin' in a concurrent statement list
libghdl: :53:55: if/use is an AMS-VHDL statement
libghdl: :54:11: '==' is not the vhdl equality, replaced by '='
libghdl: :54:11: '==' expected after expression
libghdl: :54:11: (found: '=')
libghdl: :54:11: unexpected token '=' in a primary
libghdl: :54:10: ';' is expected instead of '='
libghdl: :54:11: unexpected token '=' in a simultaneous statement list
libghdl: :56:11: '==' is not the vhdl equality, replaced by '='
libghdl: :56:11: '==' expected after expression
libghdl: :56:11: (found: '=')
libghdl: :56:11: unexpected token '=' in a primary
libghdl: :56:10: ';' is expected instead of '='
libghdl: :56:11: unexpected token '=' in a simultaneous statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd] 0:00:00.241562

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd'
libghdl processing time:  90.501 us
DOM translation time:    535.310 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_03a(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd':
      Entities:
        - Name: inline_03a
          File: inline_03a.vhd
          Position: 23:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_03a.vhd
          Position: 28:13
          Entity: inline_03a
          Declared:
            - constant fp : real := 10.0
            - constant wp : real := math_2_pi * fp
            - constant tp : real := 1.0 / wp
          Hierarchy:
          Statements:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/sum2.vhd] 0:00:00.240804

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/sum2.vhd'
DOM: Error raised in libghdl.
libghdl: :22:18: ':' expected after interface identifier
libghdl: :22:18: (found: an identifier)
libghdl: :22:21: interfaces must be separated by ';' (found ',')
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:25: ';' or ')' expected after interface
libghdl: :28:9: '==' is not the vhdl equality, replaced by '='
libghdl: :28:9: '<=' is expected instead of '='
libghdl: :28:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd] 0:00:00.250061

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd'
DOM: Error raised in libghdl.
libghdl: :31:18: ':' expected after interface identifier
libghdl: :31:18: (found: an identifier)
libghdl: :31:22: interfaces must be separated by ';' (found ',')
libghdl: :38:2: object class keyword such as 'variable' is expected
libghdl: :39:2: 'begin' is expected instead of "quantity"
libghdl: :39:11: '<=' is expected instead of "vds"
libghdl: :39:14: ';' expected at end of signal assignment
libghdl: :39:14: (found: an identifier)
libghdl: :39:22: '<=' is expected instead of "ids"
libghdl: :39:25: ';' expected at end of signal assignment
libghdl: :39:25: (found: an identifier)
libghdl: :39:34: '<=' is expected instead of "drain"
libghdl: :39:39: ';' expected at end of signal assignment
libghdl: :39:39: (found: 'to')
libghdl: :39:40: unexpected token 'to' in a concurrent statement list
libghdl: :40:11: '<=' is expected instead of "vsd"
libghdl: :40:14: ';' expected at end of signal assignment
libghdl: :40:14: (found: an identifier)
libghdl: :40:22: '<=' is expected instead of "source"
libghdl: :40:28: ';' expected at end of signal assignment
libghdl: :40:28: (found: 'to')
libghdl: :40:29: unexpected token 'to' in a concurrent statement list
libghdl: :41:11: '<=' is expected instead of "vgd"
libghdl: :41:14: ';' expected at end of signal assignment
libghdl: :41:14: (found: an identifier)
libghdl: :41:22: '<=' is expected instead of "igd"
libghdl: :41:25: ';' expected at end of signal assignment
libghdl: :41:25: (found: an identifier)
libghdl: :41:34: '<=' is expected instead of "gate"
libghdl: :41:38: ';' expected at end of signal assignment
libghdl: :41:38: (found: 'to')
libghdl: :41:39: unexpected token 'to' in a concurrent statement list
libghdl: :42:2: unexpected token 'constant' in a concurrent statement list
libghdl: :43:2: unexpected token 'constant' in a concurrent statement list
libghdl: :45:11: '<=' is expected instead of "mos_noise_source"
libghdl: :45:27: ';' expected at end of signal assignment
libghdl: :45:27: (found: ':')
libghdl: :45:28: unexpected token ':' in a concurrent statement list
libghdl: :49:0: unexpected token 'begin' in a concurrent statement list
libghdl: :51:55: if/use is an AMS-VHDL statement
libghdl: :55:12: '==' is not the vhdl equality, replaced by '='
libghdl: :55:12: '==' expected after expression
libghdl: :55:12: (found: '=')
libghdl: :55:12: unexpected token '=' in a primary
libghdl: :55:11: ';' is expected instead of '='
libghdl: :55:12: unexpected token '=' in a simultaneous statement list
libghdl: :57:12: '==' is not the vhdl equality, replaced by '='
libghdl: :57:12: '==' expected after expression
libghdl: :57:12: (found: '=')
libghdl: :57:12: unexpected token '=' in a primary
libghdl: :57:11: ';' is expected instead of '='
libghdl: :57:12: unexpected token '=' in a simultaneous statement list
libghdl: :59:12: '==' is not the vhdl equality, replaced by '='
libghdl: :59:12: '==' expected after expression
libghdl: :59:12: (found: '=')
libghdl: :59:12: unexpected token '=' in a primary
libghdl: :59:11: ';' is expected instead of '='
libghdl: :59:12: unexpected token '=' in a simultaneous statement list
libghdl: :63:12: '==' is not the vhdl equality, replaced by '='
libghdl: :63:12: '==' expected after expression
libghdl: :63:12: (found: '=')
libghdl: :63:12: unexpected token '=' in a primary
libghdl: :63:11: ';' is expected instead of '='
libghdl: :63:12: unexpected token '=' in a simultaneous statement list
libghdl: :65:12: '==' is not the vhdl equality, replaced by '='
libghdl: :65:12: '==' expected after expression
libghdl: :65:12: (found: '=')
libghdl: :65:12: unexpected token '=' in a primary
libghdl: :65:11: ';' is expected instead of '='
libghdl: :65:12: unexpected token '=' in a simultaneous statement list
libghdl: :67:12: '==' is not the vhdl equality, replaced by '='
libghdl: :67:12: '==' expected after expression
libghdl: :67:12: (found: '=')
libghdl: :67:12: unexpected token '=' in a primary
libghdl: :67:11: ';' is expected instead of '='
libghdl: :67:12: unexpected token '=' in a simultaneous statement list
libghdl: :71:8: '==' is not the vhdl equality, replaced by '='
libghdl: :71:8: '==' expected after expression
libghdl: :71:8: (found: '=')
libghdl: :71:8: unexpected token '=' in a primary
libghdl: :71:7: ';' is expected instead of '='
libghdl: :71:8: unexpected token '=' in a simultaneous statement list
libghdl: :72:8: '==' is not the vhdl equality, replaced by '='
libghdl: :72:8: '==' expected after expression
libghdl: :72:8: (found: '=')
libghdl: :72:8: unexpected token '=' in a primary
libghdl: :72:7: ';' is expected instead of '='
libghdl: :72:8: unexpected token '=' in a simultaneous statement list
libghdl: :76:8: '==' is not the vhdl equality, replaced by '='
libghdl: :76:8: '==' expected after expression
libghdl: :76:8: (found: '=')
libghdl: :76:8: unexpected token '=' in a primary
libghdl: :76:7: ';' is expected instead of '='
libghdl: :76:8: unexpected token '=' in a simultaneous statement list
libghdl: :77:8: '==' is not the vhdl equality, replaced by '='
libghdl: :77:8: '==' expected after expression
libghdl: :77:8: (found: '=')
libghdl: :77:8: unexpected token '=' in a primary
libghdl: :77:7: ';' is expected instead of '='
libghdl: :77:8: unexpected token '=' in a simultaneous statement list
libghdl: :78:8: '==' is not the vhdl equality, replaced by '='
libghdl: :78:8: '==' expected after expression
libghdl: :78:8: (found: '=')
libghdl: :78:8: unexpected token '=' in a primary
libghdl: :78:7: ';' is expected instead of '='
libghdl: :78:8: unexpected token '=' in a simultaneous statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_constant.vhd] 0:00:00.244670

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_constant.vhd'
DOM: Error raised in libghdl.
libghdl: :31:18: ':' expected after interface identifier
libghdl: :31:18: (found: an identifier)
libghdl: :31:25: ';' or ')' expected after interface
libghdl: :39:2: object class keyword such as 'variable' is expected
libghdl: :43:55: if/use is an AMS-VHDL statement
libghdl: :44:11: '==' is not the vhdl equality, replaced by '='
libghdl: :44:11: '==' expected after expression
libghdl: :44:11: (found: '=')
libghdl: :44:11: unexpected token '=' in a primary
libghdl: :44:10: ';' is expected instead of '='
libghdl: :44:11: unexpected token '=' in a simultaneous statement list
libghdl: :46:11: '==' is not the vhdl equality, replaced by '='
libghdl: :46:11: '==' expected after expression
libghdl: :46:11: (found: '=')
libghdl: :46:11: unexpected token '=' in a primary
libghdl: :46:10: ';' is expected instead of '='
libghdl: :46:11: unexpected token '=' in a simultaneous statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/gain.vhd] 0:00:00.258297

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/gain.vhd'
DOM: Error raised in libghdl.
libghdl: :22:18: ':' expected after interface identifier
libghdl: :22:18: (found: an identifier)
libghdl: :22:24: ';' or ')' expected after interface
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:25: ';' or ')' expected after interface
libghdl: :28:9: '==' is not the vhdl equality, replaced by '='
libghdl: :28:9: '<=' is expected instead of '='
libghdl: :28:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd] 0:00:00.248290

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd'
DOM: Error raised in libghdl.
libghdl: :67:18: ':' expected after interface identifier
libghdl: :67:18: (found: an identifier)
libghdl: :67:24: ';' or ')' expected after interface
libghdl: :68:13: ':' expected after interface identifier
libghdl: :68:13: (found: an identifier)
libghdl: :68:18: ';' or ')' expected after interface
libghdl: :77:2: object class keyword such as 'variable' is expected
libghdl: :79:2: 'begin' is expected instead of "quantity"
libghdl: :79:11: '<=' is expected instead of "theta"
libghdl: :79:16: ';' expected at end of signal assignment
libghdl: :79:16: (found: an identifier)
libghdl: :79:24: '<=' is expected instead of "torq_ang"
libghdl: :79:32: ';' expected at end of signal assignment
libghdl: :79:32: (found: an identifier)
libghdl: :79:41: '<=' is expected instead of "rot2"
libghdl: :79:45: ';' expected at end of signal assignment
libghdl: :79:45: (found: 'to')
libghdl: :79:46: unexpected token 'to' in a concurrent statement list
libghdl: :81:0: unexpected token 'begin' in a concurrent statement list
libghdl: :84:8: '==' is not the vhdl equality, replaced by '='
libghdl: :85:11: '==' is not the vhdl equality, replaced by '='
libghdl: :85:11: '<=' is expected instead of '='
libghdl: :85:11: unexpected token '=' in a primary
libghdl: :112:13: ':' expected after interface identifier
libghdl: :112:13: (found: an identifier)
libghdl: :112:21: ';' or ')' expected after interface
libghdl: :113:13: ':' expected after interface identifier
libghdl: :113:13: (found: an identifier)
libghdl: :113:23: ';' or ')' expected after interface
libghdl: :118:0: object class keyword such as 'variable' is expected
libghdl: :119:0: 'begin' is expected instead of "quantity"
libghdl: :119:9: '<=' is expected instead of "v_out"
libghdl: :119:14: ';' expected at end of signal assignment
libghdl: :119:14: (found: an identifier)
libghdl: :119:22: '<=' is expected instead of "out_i"
libghdl: :119:27: ';' expected at end of signal assignment
libghdl: :119:27: (found: an identifier)
libghdl: :119:36: '<=' is expected instead of "output"
libghdl: :119:42: ';' expected at end of signal assignment
libghdl: :119:42: (found: 'to')
libghdl: :119:43: unexpected token 'to' in a concurrent statement list
libghdl: :121:2: unexpected token 'begin' in a concurrent statement list
libghdl: :122:9: '==' is not the vhdl equality, replaced by '='
libghdl: :150:13: ':' expected after interface identifier
libghdl: :150:13: (found: an identifier)
libghdl: :150:22: ';' or ')' expected after interface
libghdl: :151:13: ':' expected after interface identifier
libghdl: :151:13: (found: an identifier)
libghdl: :151:19: ';' or ')' expected after interface
libghdl: :157:2: object class keyword such as 'variable' is expected
libghdl: :158:2: 'begin' is expected instead of "quantity"
libghdl: :158:11: '<=' is expected instead of "tran"
libghdl: :158:15: ';' expected at end of signal assignment
libghdl: :158:15: (found: an identifier)
libghdl: :158:23: '<=' is expected instead of "tran_frc"
libghdl: :158:31: ';' expected at end of signal assignment
libghdl: :158:31: (found: an identifier)
libghdl: :158:40: '<=' is expected instead of "pos"
libghdl: :158:43: ';' expected at end of signal assignment
libghdl: :158:43: (found: 'to')
libghdl: :158:44: unexpected token 'to' in a concurrent statement list
libghdl: :160:2: unexpected token 'begin' in a concurrent statement list
libghdl: :161:8: '==' is not the vhdl equality, replaced by '='
libghdl: :162:12: '==' is not the vhdl equality, replaced by '='
libghdl: :162:12: '<=' is expected instead of '='
libghdl: :162:12: unexpected token '=' in a primary
libghdl: :190:13: ':' expected after interface identifier
libghdl: :190:13: (found: an identifier)
libghdl: :190:20: ';' or ')' expected after interface
libghdl: :191:13: ':' expected after interface identifier
libghdl: :191:13: (found: an identifier)
libghdl: :191:21: ';' or ')' expected after interface
libghdl: :197:2: object class keyword such as 'variable' is expected
libghdl: :198:2: 'begin' is expected instead of "quantity"
libghdl: :198:11: '<=' is expected instead of "rot"
libghdl: :198:14: ';' expected at end of signal assignment
libghdl: :198:14: (found: an identifier)
libghdl: :198:22: '<=' is expected instead of "rot_tq"
libghdl: :198:28: ';' expected at end of signal assignment
libghdl: :198:28: (found: an identifier)
libghdl: :198:37: '<=' is expected instead of "theta"
libghdl: :198:42: ';' expected at end of signal assignment
libghdl: :198:42: (found: 'to')
libghdl: :198:43: unexpected token 'to' in a concurrent statement list
libghdl: :200:2: unexpected token 'begin' in a concurrent statement list
libghdl: :201:7: '==' is not the vhdl equality, replaced by '='
libghdl: :202:10: '==' is not the vhdl equality, replaced by '='
libghdl: :202:10: '<=' is expected instead of '='
libghdl: :202:10: unexpected token '=' in a primary
libghdl: :258:17: ':' expected after interface identifier
libghdl: :258:17: (found: an identifier)
libghdl: :258:19: interfaces must be separated by ';' (found ',')
libghdl: :259:17: ':' expected after interface identifier
libghdl: :259:17: (found: an identifier)
libghdl: :259:28: ';' or ')' expected after interface
libghdl: :270:2: object class keyword such as 'variable' is expected
libghdl: :271:2: 'begin' is expected instead of "quantity"
libghdl: :271:11: '<=' is expected instead of "w"
libghdl: :271:12: ';' expected at end of signal assignment
libghdl: :271:12: (found: an identifier)
libghdl: :271:20: '<=' is expected instead of "torq"
libghdl: :271:24: ';' expected at end of signal assignment
libghdl: :271:24: (found: an identifier)
libghdl: :271:33: '<=' is expected instead of "shaft_rotv"
libghdl: :271:43: ';' expected at end of signal assignment
libghdl: :271:43: (found: 'to')
libghdl: :271:44: unexpected token 'to' in a concurrent statement list
libghdl: :273:0: unexpected token 'begin' in a concurrent statement list
libghdl: :275:7: '==' is not the vhdl equality, replaced by '='
libghdl: :276:5: '==' is not the vhdl equality, replaced by '='
libghdl: :276:5: '<=' is expected instead of '='
libghdl: :276:5: unexpected token '=' in a primary
libghdl: :341:18: ':' expected after interface identifier
libghdl: :341:18: (found: an identifier)
libghdl: :341:22: interfaces must be separated by ';' (found ',')
libghdl: :347:2: object class keyword such as 'variable' is expected
libghdl: :348:2: 'begin' is expected instead of "quantity"
libghdl: :348:11: '<=' is expected instead of "ang"
libghdl: :348:14: ';' expected at end of signal assignment
libghdl: :348:14: (found: an identifier)
libghdl: :348:22: '<=' is expected instead of "trq"
libghdl: :348:25: ';' expected at end of signal assignment
libghdl: :348:25: (found: an identifier)
libghdl: :348:34: '<=' is expected instead of "ang1"
libghdl: :348:38: ';' expected at end of signal assignment
libghdl: :348:38: (found: 'to')
libghdl: :348:39: unexpected token 'to' in a concurrent statement list
libghdl: :350:0: unexpected token 'begin' in a concurrent statement list
libghdl: :352:11: '==' is not the vhdl equality, replaced by '='
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/clock_duty.vhd] 0:00:00.253206

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/clock_duty.vhd'
libghdl processing time:  96.602 us
DOM translation time:    949.616 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - clock_duty(ideal)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/clock_duty.vhd':
      Entities:
        - Name: clock_duty
          File: clock_duty.vhd
          Position: 25:7
          Generics:
            - on_time : in time := 20 us
            - off_time : in time := 19.98 ms
          Ports:
            - clock_out : out std_logic := Z
          Declared:
          Statements:
          Architecures:
          - ideal
      Architectures:
        - Name: ideal
          File: clock_duty.vhd
          Position: 35:13
          Entity: clock_duty
          Declared:
          Hierarchy:
            - None: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_diff.vhd] 0:00:00.240306

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_diff.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:24: ';' or ')' expected after interface
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:25: ';' or ')' expected after interface
libghdl: :48:9: '==' is not the vhdl equality, replaced by '='
libghdl: :48:9: '<=' is expected instead of '='
libghdl: :48:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd] 0:00:00.259872

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd'
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] procedure declaration without body
[NOT IMPLEMENTED] Array_Subtype_Definition
libghdl processing time:  242.005 us
DOM translation time:    1022.718 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
        - stimulus_generators
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd':
      Entities:
      Architectures:
      Packages:
        - Name: stimulus_generators
          File: stimulus_generators.vhd
          Position: 22:8
          Declared:
      PackageBodies:
        - Name: stimulus_generators
          Declared:
          - type ???? is array(........) of .....
          - constant digit : digit_table := (0, 1)
          - function natural_to_bv return bit_vector
          - procedure all_possible_values
          - procedure all_possible_values
          - procedure all_possible_values
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/sum2.vhd] 0:00:00.244387

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/sum2.vhd'
DOM: Error raised in libghdl.
libghdl: :22:18: ':' expected after interface identifier
libghdl: :22:18: (found: an identifier)
libghdl: :22:21: interfaces must be separated by ';' (found ',')
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:25: ';' or ')' expected after interface
libghdl: :31:9: '==' is not the vhdl equality, replaced by '='
libghdl: :31:9: '<=' is expected instead of '='
libghdl: :31:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_sine.vhd] 0:00:00.259480

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_sine.vhd'
DOM: Error raised in libghdl.
libghdl: :33:18: ':' expected after interface identifier
libghdl: :33:18: (found: an identifier)
libghdl: :33:25: ';' or ')' expected after interface
libghdl: :41:2: object class keyword such as 'variable' is expected
libghdl: :43:2: 'begin' is expected instead of "quantity"
libghdl: :43:11: '<=' is expected instead of "ac_spec"
libghdl: :43:18: ';' expected at end of signal assignment
libghdl: :43:18: (found: ':')
libghdl: :43:19: unexpected token ':' in a concurrent statement list
libghdl: :45:0: unexpected token 'begin' in a concurrent statement list
libghdl: :48:12: '==' is not the vhdl equality, replaced by '='
libghdl: :50:55: if/use is an AMS-VHDL statement
libghdl: :51:11: '==' is not the vhdl equality, replaced by '='
libghdl: :51:11: '==' expected after expression
libghdl: :51:11: (found: '=')
libghdl: :51:11: unexpected token '=' in a primary
libghdl: :51:10: ';' is expected instead of '='
libghdl: :51:11: unexpected token '=' in a simultaneous statement list
libghdl: :53:11: '==' is not the vhdl equality, replaced by '='
libghdl: :53:11: '==' expected after expression
libghdl: :53:11: (found: '=')
libghdl: :53:11: unexpected token '=' in a primary
libghdl: :53:10: ';' is expected instead of '='
libghdl: :53:11: unexpected token '=' in a simultaneous statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd] 0:00:00.240461

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd'
DOM: Error raised in libghdl.
libghdl: :30:18: ':' expected after interface identifier
libghdl: :30:18: (found: an identifier)
libghdl: :30:24: ';' or ')' expected after interface
libghdl: :31:18: ':' expected after interface identifier
libghdl: :31:18: (found: an identifier)
libghdl: :31:25: ';' or ')' expected after interface
libghdl: :44:9: '==' is not the vhdl equality, replaced by '='
libghdl: :44:9: '<=' is expected instead of '='
libghdl: :44:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd] 0:00:00.254271

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd'
DOM: Error raised in libghdl.
libghdl: :37:13: ':' expected after interface identifier
libghdl: :37:13: (found: an identifier)
libghdl: :37:16: interfaces must be separated by ';' (found ',')
libghdl: :46:2: object class keyword such as 'variable' is expected
libghdl: :48:2: 'begin' is expected instead of "quantity"
libghdl: :48:11: '<=' is expected instead of "phase_rad"
libghdl: :48:20: ';' expected at end of signal assignment
libghdl: :48:20: (found: ':')
libghdl: :48:21: unexpected token ':' in a concurrent statement list
libghdl: :50:11: '<=' is expected instead of "ac_spec"
libghdl: :50:18: ';' expected at end of signal assignment
libghdl: :50:18: (found: ':')
libghdl: :50:21: unexpected token ':' in a concurrent statement list
libghdl: :52:0: unexpected token 'begin' in a concurrent statement list
libghdl: :54:12: '==' is not the vhdl equality, replaced by '='
libghdl: :56:55: if/use is an AMS-VHDL statement
libghdl: :57:6: '==' is not the vhdl equality, replaced by '='
libghdl: :57:6: '==' expected after expression
libghdl: :57:6: (found: '=')
libghdl: :57:6: unexpected token '=' in a primary
libghdl: :57:5: ';' is expected instead of '='
libghdl: :57:6: unexpected token '=' in a simultaneous statement list
libghdl: :59:6: '==' is not the vhdl equality, replaced by '='
libghdl: :59:6: '==' expected after expression
libghdl: :59:6: (found: '=')
libghdl: :59:6: unexpected token '=' in a primary
libghdl: :59:5: ';' is expected instead of '='
libghdl: :59:6: unexpected token '=' in a simultaneous statement list
libghdl: :77:18: ':' expected after interface identifier
libghdl: :77:18: (found: an identifier)
libghdl: :77:21: interfaces must be separated by ';' (found ',')
libghdl: :78:12: ':' expected after interface identifier
libghdl: :78:12: (found: an identifier)
libghdl: :78:18: ';' or ')' expected after interface
libghdl: :82:2: object class keyword such as 'variable' is expected
libghdl: :83:2: 'begin' is expected instead of "quantity"
libghdl: :83:11: '<=' is expected instead of "vin2"
libghdl: :83:15: ';' expected at end of signal assignment
libghdl: :83:15: (found: an identifier)
libghdl: :83:23: '<=' is expected instead of "in2"
libghdl: :83:26: ';' expected at end of signal assignment
libghdl: :83:26: (found: 'to')
libghdl: :83:27: unexpected token 'to' in a concurrent statement list
libghdl: :84:11: '<=' is expected instead of "vout"
libghdl: :84:15: ';' expected at end of signal assignment
libghdl: :84:15: (found: an identifier)
libghdl: :84:23: '<=' is expected instead of "iout"
libghdl: :84:27: ';' expected at end of signal assignment
libghdl: :84:27: (found: an identifier)
libghdl: :84:36: '<=' is expected instead of "output"
libghdl: :84:42: ';' expected at end of signal assignment
libghdl: :84:42: (found: 'to')
libghdl: :84:43: unexpected token 'to' in a concurrent statement list
libghdl: :86:0: unexpected token 'begin' in a concurrent statement list
libghdl: :87:6: '==' is not the vhdl equality, replaced by '='
libghdl: :112:18: ':' expected after interface identifier
libghdl: :112:18: (found: an identifier)
libghdl: :112:23: ';' or ')' expected after interface
libghdl: :113:12: ':' expected after interface identifier
libghdl: :113:12: (found: an identifier)
libghdl: :113:18: ';' or ')' expected after interface
libghdl: :117:2: object class keyword such as 'variable' is expected
libghdl: :118:2: 'begin' is expected instead of "quantity"
libghdl: :118:11: '<=' is expected instead of "vout"
libghdl: :118:15: ';' expected at end of signal assignment
libghdl: :118:15: (found: an identifier)
libghdl: :118:23: '<=' is expected instead of "iout"
libghdl: :118:27: ';' expected at end of signal assignment
libghdl: :118:27: (found: an identifier)
libghdl: :118:36: '<=' is expected instead of "output"
libghdl: :118:42: ';' expected at end of signal assignment
libghdl: :118:42: (found: 'to')
libghdl: :118:43: unexpected token 'to' in a concurrent statement list
libghdl: :120:10: '<=' is expected instead of "vin_temp"
libghdl: :120:18: ';' expected at end of signal assignment
libghdl: :120:18: (found: ':')
libghdl: :120:19: unexpected token ':' in a concurrent statement list
libghdl: :121:1: unexpected token 'constant' in a concurrent statement list
libghdl: :122:1: unexpected token 'constant' in a concurrent statement list
libghdl: :123:1: unexpected token 'constant' in a concurrent statement list
libghdl: :124:1: unexpected token 'constant' in a concurrent statement list
libghdl: :125:0: unexpected token 'begin' in a concurrent statement list
libghdl: :126:10: '==' is not the vhdl equality, replaced by '='
libghdl: :127:6: '==' is not the vhdl equality, replaced by '='
libghdl: :127:6: '<=' is expected instead of '='
libghdl: :127:6: unexpected token '=' in a primary
libghdl: :139:18: ':' expected after interface identifier
libghdl: :139:18: (found: an identifier)
libghdl: :139:24: ';' or ')' expected after interface
libghdl: :140:12: ':' expected after interface identifier
libghdl: :140:12: (found: an identifier)
libghdl: :140:18: ';' or ')' expected after interface
libghdl: :145:2: object class keyword such as 'variable' is expected
libghdl: :146:2: 'begin' is expected instead of "quantity"
libghdl: :146:11: '<=' is expected instead of "vout"
libghdl: :146:15: ';' expected at end of signal assignment
libghdl: :146:15: (found: an identifier)
libghdl: :146:23: '<=' is expected instead of "iout"
libghdl: :146:27: ';' expected at end of signal assignment
libghdl: :146:27: (found: an identifier)
libghdl: :146:36: '<=' is expected instead of "output"
libghdl: :146:42: ';' expected at end of signal assignment
libghdl: :146:42: (found: 'to')
libghdl: :146:43: unexpected token 'to' in a concurrent statement list
libghdl: :148:0: unexpected token 'begin' in a concurrent statement list
libghdl: :149:6: '==' is not the vhdl equality, replaced by '='
libghdl: :164:11: ':' expected after interface identifier
libghdl: :164:11: (found: an identifier)
libghdl: :164:16: ';' or ')' expected after interface
libghdl: :165:11: ':' expected after interface identifier
libghdl: :165:11: (found: an identifier)
libghdl: :165:17: ';' or ')' expected after interface
libghdl: :169:3: object class keyword such as 'variable' is expected
libghdl: :170:3: 'begin' is expected instead of "quantity"
libghdl: :170:12: '<=' is expected instead of "vout"
libghdl: :170:16: ';' expected at end of signal assignment
libghdl: :170:16: (found: an identifier)
libghdl: :170:24: '<=' is expected instead of "iout"
libghdl: :170:28: ';' expected at end of signal assignment
libghdl: :170:28: (found: an identifier)
libghdl: :170:37: '<=' is expected instead of "output"
libghdl: :170:43: ';' expected at end of signal assignment
libghdl: :170:43: (found: 'to')
libghdl: :170:44: unexpected token 'to' in a concurrent statement list
libghdl: :171:1: unexpected token 'constant' in a concurrent statement list
libghdl: :172:0: unexpected token 'begin' in a concurrent statement list
libghdl: :173:21: if/use is an AMS-VHDL statement
libghdl: :174:7: '==' is not the vhdl equality, replaced by '='
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd] 0:00:00.241324

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:24: ';' or ')' expected after interface
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:25: ';' or ')' expected after interface
libghdl: :33:24: if/use is an AMS-VHDL statement
libghdl: :34:11: '==' is not the vhdl equality, replaced by '='
libghdl: :34:11: '==' expected after expression
libghdl: :34:11: (found: '=')
libghdl: :34:11: unexpected token '=' in a primary
libghdl: :34:10: ';' is expected instead of '='
libghdl: :34:11: unexpected token '=' in a simultaneous statement list
libghdl: :36:11: '==' is not the vhdl equality, replaced by '='
libghdl: :36:11: '==' expected after expression
libghdl: :36:11: (found: '=')
libghdl: :36:11: unexpected token '=' in a primary
libghdl: :36:10: ';' is expected instead of '='
libghdl: :36:11: unexpected token '=' in a simultaneous statement list
libghdl: :38:11: '==' is not the vhdl equality, replaced by '='
libghdl: :38:11: '==' expected after expression
libghdl: :38:11: (found: '=')
libghdl: :38:11: unexpected token '=' in a primary
libghdl: :38:10: ';' is expected instead of '='
libghdl: :38:11: unexpected token '=' in a simultaneous statement list
libghdl: :41:8: '<=' is expected instead of 'on'
libghdl: :41:8: unexpected token 'on' in a primary
libghdl: :41:7: ';' expected at end of signal assignment
libghdl: :41:7: (found: 'on')
libghdl: :41:8: unexpected token 'on' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain.vhd] 0:00:00.251211

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain.vhd'
DOM: Error raised in libghdl.
libghdl: :22:18: ':' expected after interface identifier
libghdl: :22:18: (found: an identifier)
libghdl: :22:24: ';' or ')' expected after interface
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:25: ';' or ')' expected after interface
libghdl: :31:9: '==' is not the vhdl equality, replaced by '='
libghdl: :31:9: '<=' is expected instead of '='
libghdl: :31:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd] 0:00:00.235801

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd'
DOM: Error raised in libghdl.
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:22: interfaces must be separated by ';' (found ',')
libghdl: :34:2: object class keyword such as 'variable' is expected
libghdl: :35:2: 'begin' is expected instead of "quantity"
libghdl: :35:11: '<=' is expected instead of "ang"
libghdl: :35:14: ';' expected at end of signal assignment
libghdl: :35:14: (found: an identifier)
libghdl: :35:22: '<=' is expected instead of "trq"
libghdl: :35:25: ';' expected at end of signal assignment
libghdl: :35:25: (found: an identifier)
libghdl: :35:34: '<=' is expected instead of "ang1"
libghdl: :35:38: ';' expected at end of signal assignment
libghdl: :35:38: (found: 'to')
libghdl: :35:39: unexpected token 'to' in a concurrent statement list
libghdl: :37:0: unexpected token 'begin' in a concurrent statement list
libghdl: :39:12: '==' is not the vhdl equality, replaced by '='
libghdl: :41:19: if/use is an AMS-VHDL statement
libghdl: :42:8: '==' is not the vhdl equality, replaced by '='
libghdl: :42:8: '==' expected after expression
libghdl: :42:8: (found: '=')
libghdl: :42:8: unexpected token '=' in a primary
libghdl: :42:7: ';' is expected instead of '='
libghdl: :42:8: unexpected token '=' in a simultaneous statement list
libghdl: :44:10: '==' is not the vhdl equality, replaced by '='
libghdl: :44:10: '==' expected after expression
libghdl: :44:10: (found: '=')
libghdl: :44:10: unexpected token '=' in a primary
libghdl: :44:7: ';' is expected instead of '='
libghdl: :44:10: unexpected token '=' in a simultaneous statement list
libghdl: :46:10: '==' is not the vhdl equality, replaced by '='
libghdl: :46:10: '==' expected after expression
libghdl: :46:10: (found: '=')
libghdl: :46:10: unexpected token '=' in a primary
libghdl: :46:7: ';' is expected instead of '='
libghdl: :46:10: unexpected token '=' in a simultaneous statement list
libghdl: :49:8: '<=' is expected instead of 'on'
libghdl: :49:8: unexpected token 'on' in a primary
libghdl: :49:7: ';' expected at end of signal assignment
libghdl: :49:7: (found: 'on')
libghdl: :49:8: unexpected token 'on' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd] 0:00:00.242639

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd'
DOM: Error raised in libghdl.
libghdl: :67:18: ':' expected after interface identifier
libghdl: :67:18: (found: an identifier)
libghdl: :67:24: ';' or ')' expected after interface
libghdl: :68:13: ':' expected after interface identifier
libghdl: :68:13: (found: an identifier)
libghdl: :68:18: ';' or ')' expected after interface
libghdl: :77:2: object class keyword such as 'variable' is expected
libghdl: :79:2: 'begin' is expected instead of "quantity"
libghdl: :79:11: '<=' is expected instead of "theta"
libghdl: :79:16: ';' expected at end of signal assignment
libghdl: :79:16: (found: an identifier)
libghdl: :79:24: '<=' is expected instead of "torq_ang"
libghdl: :79:32: ';' expected at end of signal assignment
libghdl: :79:32: (found: an identifier)
libghdl: :79:41: '<=' is expected instead of "rot2"
libghdl: :79:45: ';' expected at end of signal assignment
libghdl: :79:45: (found: 'to')
libghdl: :79:46: unexpected token 'to' in a concurrent statement list
libghdl: :81:0: unexpected token 'begin' in a concurrent statement list
libghdl: :84:8: '==' is not the vhdl equality, replaced by '='
libghdl: :85:11: '==' is not the vhdl equality, replaced by '='
libghdl: :85:11: '<=' is expected instead of '='
libghdl: :85:11: unexpected token '=' in a primary
libghdl: :112:13: ':' expected after interface identifier
libghdl: :112:13: (found: an identifier)
libghdl: :112:21: ';' or ')' expected after interface
libghdl: :113:13: ':' expected after interface identifier
libghdl: :113:13: (found: an identifier)
libghdl: :113:23: ';' or ')' expected after interface
libghdl: :118:0: object class keyword such as 'variable' is expected
libghdl: :119:0: 'begin' is expected instead of "quantity"
libghdl: :119:9: '<=' is expected instead of "v_out"
libghdl: :119:14: ';' expected at end of signal assignment
libghdl: :119:14: (found: an identifier)
libghdl: :119:22: '<=' is expected instead of "out_i"
libghdl: :119:27: ';' expected at end of signal assignment
libghdl: :119:27: (found: an identifier)
libghdl: :119:36: '<=' is expected instead of "output"
libghdl: :119:42: ';' expected at end of signal assignment
libghdl: :119:42: (found: 'to')
libghdl: :119:43: unexpected token 'to' in a concurrent statement list
libghdl: :121:2: unexpected token 'begin' in a concurrent statement list
libghdl: :122:9: '==' is not the vhdl equality, replaced by '='
libghdl: :150:13: ':' expected after interface identifier
libghdl: :150:13: (found: an identifier)
libghdl: :150:22: ';' or ')' expected after interface
libghdl: :151:13: ':' expected after interface identifier
libghdl: :151:13: (found: an identifier)
libghdl: :151:19: ';' or ')' expected after interface
libghdl: :157:2: object class keyword such as 'variable' is expected
libghdl: :158:2: 'begin' is expected instead of "quantity"
libghdl: :158:11: '<=' is expected instead of "tran"
libghdl: :158:15: ';' expected at end of signal assignment
libghdl: :158:15: (found: an identifier)
libghdl: :158:23: '<=' is expected instead of "tran_frc"
libghdl: :158:31: ';' expected at end of signal assignment
libghdl: :158:31: (found: an identifier)
libghdl: :158:40: '<=' is expected instead of "pos"
libghdl: :158:43: ';' expected at end of signal assignment
libghdl: :158:43: (found: 'to')
libghdl: :158:44: unexpected token 'to' in a concurrent statement list
libghdl: :160:2: unexpected token 'begin' in a concurrent statement list
libghdl: :161:8: '==' is not the vhdl equality, replaced by '='
libghdl: :162:12: '==' is not the vhdl equality, replaced by '='
libghdl: :162:12: '<=' is expected instead of '='
libghdl: :162:12: unexpected token '=' in a primary
libghdl: :190:13: ':' expected after interface identifier
libghdl: :190:13: (found: an identifier)
libghdl: :190:20: ';' or ')' expected after interface
libghdl: :191:13: ':' expected after interface identifier
libghdl: :191:13: (found: an identifier)
libghdl: :191:21: ';' or ')' expected after interface
libghdl: :197:2: object class keyword such as 'variable' is expected
libghdl: :198:2: 'begin' is expected instead of "quantity"
libghdl: :198:11: '<=' is expected instead of "rot"
libghdl: :198:14: ';' expected at end of signal assignment
libghdl: :198:14: (found: an identifier)
libghdl: :198:22: '<=' is expected instead of "rot_tq"
libghdl: :198:28: ';' expected at end of signal assignment
libghdl: :198:28: (found: an identifier)
libghdl: :198:37: '<=' is expected instead of "theta"
libghdl: :198:42: ';' expected at end of signal assignment
libghdl: :198:42: (found: 'to')
libghdl: :198:43: unexpected token 'to' in a concurrent statement list
libghdl: :200:2: unexpected token 'begin' in a concurrent statement list
libghdl: :201:7: '==' is not the vhdl equality, replaced by '='
libghdl: :202:10: '==' is not the vhdl equality, replaced by '='
libghdl: :202:10: '<=' is expected instead of '='
libghdl: :202:10: unexpected token '=' in a primary
libghdl: :258:17: ':' expected after interface identifier
libghdl: :258:17: (found: an identifier)
libghdl: :258:19: interfaces must be separated by ';' (found ',')
libghdl: :259:17: ':' expected after interface identifier
libghdl: :259:17: (found: an identifier)
libghdl: :259:28: ';' or ')' expected after interface
libghdl: :270:2: object class keyword such as 'variable' is expected
libghdl: :271:2: 'begin' is expected instead of "quantity"
libghdl: :271:11: '<=' is expected instead of "w"
libghdl: :271:12: ';' expected at end of signal assignment
libghdl: :271:12: (found: an identifier)
libghdl: :271:20: '<=' is expected instead of "torq"
libghdl: :271:24: ';' expected at end of signal assignment
libghdl: :271:24: (found: an identifier)
libghdl: :271:33: '<=' is expected instead of "shaft_rotv"
libghdl: :271:43: ';' expected at end of signal assignment
libghdl: :271:43: (found: 'to')
libghdl: :271:44: unexpected token 'to' in a concurrent statement list
libghdl: :273:0: unexpected token 'begin' in a concurrent statement list
libghdl: :275:7: '==' is not the vhdl equality, replaced by '='
libghdl: :276:5: '==' is not the vhdl equality, replaced by '='
libghdl: :276:5: '<=' is expected instead of '='
libghdl: :276:5: unexpected token '=' in a primary
libghdl: :341:18: ':' expected after interface identifier
libghdl: :341:18: (found: an identifier)
libghdl: :341:22: interfaces must be separated by ';' (found ',')
libghdl: :347:2: object class keyword such as 'variable' is expected
libghdl: :348:2: 'begin' is expected instead of "quantity"
libghdl: :348:11: '<=' is expected instead of "ang"
libghdl: :348:14: ';' expected at end of signal assignment
libghdl: :348:14: (found: an identifier)
libghdl: :348:22: '<=' is expected instead of "trq"
libghdl: :348:25: ';' expected at end of signal assignment
libghdl: :348:25: (found: an identifier)
libghdl: :348:34: '<=' is expected instead of "ang1"
libghdl: :348:38: ';' expected at end of signal assignment
libghdl: :348:38: (found: 'to')
libghdl: :348:39: unexpected token 'to' in a concurrent statement list
libghdl: :350:0: unexpected token 'begin' in a concurrent statement list
libghdl: :352:11: '==' is not the vhdl equality, replaced by '='
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gear_rv_r.vhd] 0:00:00.236872

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gear_rv_r.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:24: ';' or ')' expected after interface
libghdl: :26:18: ':' expected after interface identifier
libghdl: :26:18: (found: an identifier)
libghdl: :26:23: ';' or ')' expected after interface
libghdl: :33:2: object class keyword such as 'variable' is expected
libghdl: :34:2: 'begin' is expected instead of "quantity"
libghdl: :34:11: '<=' is expected instead of "theta"
libghdl: :34:16: ';' expected at end of signal assignment
libghdl: :34:16: (found: an identifier)
libghdl: :34:24: '<=' is expected instead of "torq_ang"
libghdl: :34:32: ';' expected at end of signal assignment
libghdl: :34:32: (found: an identifier)
libghdl: :34:41: '<=' is expected instead of "rot2"
libghdl: :34:45: ';' expected at end of signal assignment
libghdl: :34:45: (found: 'to')
libghdl: :34:46: unexpected token 'to' in a concurrent statement list
libghdl: :36:0: unexpected token 'begin' in a concurrent statement list
libghdl: :38:9: '==' is not the vhdl equality, replaced by '='
libghdl: :39:11: '==' is not the vhdl equality, replaced by '='
libghdl: :39:11: '<=' is expected instead of '='
libghdl: :39:11: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain_e.vhd] 0:00:00.235906

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain_e.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:24: ';' or ')' expected after interface
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:25: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "vout"
libghdl: :33:15: ';' expected at end of signal assignment
libghdl: :33:15: (found: an identifier)
libghdl: :33:23: '<=' is expected instead of "iout"
libghdl: :33:27: ';' expected at end of signal assignment
libghdl: :33:27: (found: an identifier)
libghdl: :33:36: '<=' is expected instead of "output"
libghdl: :33:42: ';' expected at end of signal assignment
libghdl: :33:42: (found: 'to')
libghdl: :33:43: unexpected token 'to' in a concurrent statement list
libghdl: :35:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:7: '==' is not the vhdl equality, replaced by '='

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd] 0:00:00.258067

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd'
libghdl processing time:  108.702 us
DOM translation time:    1024.918 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - dff(behav)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd':
      Entities:
        - Name: dff
          File: dff.vhd
          Position: 22:7
          Generics:
          Ports:
            - d, clk : in std_ulogic
            - q : out std_ulogic
          Declared:
          Statements:
          Architecures:
          - behav
      Architectures:
        - Name: behav
          File: dff.vhd
          Position: 28:13
          Entity: dff
          Declared:
          Hierarchy:
            - storage: process(...)
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lpf_1.vhd] 0:00:00.240599

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lpf_1.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:24: ';' or ')' expected after interface
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:25: ';' or ')' expected after interface
libghdl: :41:9: '==' is not the vhdl equality, replaced by '='
libghdl: :41:9: '<=' is expected instead of '='
libghdl: :41:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd] 0:00:00.224432

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:22: interfaces must be separated by ';' (found ',')
libghdl: :30:2: object class keyword such as 'variable' is expected
libghdl: :32:4: '==' is not the vhdl equality, replaced by '='
libghdl: :32:4: '<=' is expected instead of '='
libghdl: :32:4: unexpected token '=' in a primary
libghdl: :39:2: object class keyword such as 'variable' is expected
libghdl: :41:4: '==' is not the vhdl equality, replaced by '='
libghdl: :41:4: '<=' is expected instead of '='
libghdl: :41:4: unexpected token '=' in a primary
libghdl: :58:2: object class keyword such as 'variable' is expected
libghdl: :64:17: if/use is an AMS-VHDL statement
libghdl: :65:7: '==' is not the vhdl equality, replaced by '='
libghdl: :65:7: '==' expected after expression
libghdl: :65:7: (found: '=')
libghdl: :65:7: unexpected token '=' in a primary
libghdl: :65:6: ';' is expected instead of '='
libghdl: :65:7: unexpected token '=' in a simultaneous statement list
libghdl: :66:7: '==' is not the vhdl equality, replaced by '='
libghdl: :66:7: '==' expected after expression
libghdl: :66:7: (found: '=')
libghdl: :66:7: unexpected token '=' in a primary
libghdl: :66:6: ';' is expected instead of '='
libghdl: :66:7: unexpected token '=' in a simultaneous statement list
libghdl: :68:7: '==' is not the vhdl equality, replaced by '='
libghdl: :68:7: '==' expected after expression
libghdl: :68:7: (found: '=')
libghdl: :68:7: unexpected token '=' in a primary
libghdl: :68:6: ';' is expected instead of '='
libghdl: :68:7: unexpected token '=' in a simultaneous statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag.vhd] 0:00:00.225942

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag.vhd'
DOM: Error raised in libghdl.
libghdl: :26:18: ':' expected after interface identifier
libghdl: :26:18: (found: an identifier)
libghdl: :26:24: ';' or ')' expected after interface
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:25: ';' or ')' expected after interface
libghdl: :39:9: '==' is not the vhdl equality, replaced by '='
libghdl: :39:9: '<=' is expected instead of '='
libghdl: :39:9: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd] 0:00:00.226016

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd'
DOM: Error raised in libghdl.
libghdl: :41:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd] 0:00:00.239414

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd'
DOM: Error raised in libghdl.
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:21: interfaces must be separated by ';' (found ',')
libghdl: :28:12: ':' expected after interface identifier
libghdl: :28:12: (found: an identifier)
libghdl: :28:18: ';' or ')' expected after interface
libghdl: :32:2: object class keyword such as 'variable' is expected
libghdl: :33:2: 'begin' is expected instead of "quantity"
libghdl: :33:11: '<=' is expected instead of "vin2"
libghdl: :33:15: ';' expected at end of signal assignment
libghdl: :33:15: (found: an identifier)
libghdl: :33:23: '<=' is expected instead of "in2"
libghdl: :33:26: ';' expected at end of signal assignment
libghdl: :33:26: (found: 'to')
libghdl: :33:27: unexpected token 'to' in a concurrent statement list
libghdl: :34:11: '<=' is expected instead of "vout"
libghdl: :34:15: ';' expected at end of signal assignment
libghdl: :34:15: (found: an identifier)
libghdl: :34:23: '<=' is expected instead of "iout"
libghdl: :34:27: ';' expected at end of signal assignment
libghdl: :34:27: (found: an identifier)
libghdl: :34:36: '<=' is expected instead of "output"
libghdl: :34:42: ';' expected at end of signal assignment
libghdl: :34:42: (found: 'to')
libghdl: :34:43: unexpected token 'to' in a concurrent statement list
libghdl: :36:0: unexpected token 'begin' in a concurrent statement list
libghdl: :37:6: '==' is not the vhdl equality, replaced by '='
libghdl: :49:18: ':' expected after interface identifier
libghdl: :49:18: (found: an identifier)
libghdl: :49:24: ';' or ')' expected after interface
libghdl: :50:12: ':' expected after interface identifier
libghdl: :50:12: (found: an identifier)
libghdl: :50:18: ';' or ')' expected after interface
libghdl: :55:2: object class keyword such as 'variable' is expected
libghdl: :56:2: 'begin' is expected instead of "quantity"
libghdl: :56:11: '<=' is expected instead of "vout"
libghdl: :56:15: ';' expected at end of signal assignment
libghdl: :56:15: (found: an identifier)
libghdl: :56:23: '<=' is expected instead of "iout"
libghdl: :56:27: ';' expected at end of signal assignment
libghdl: :56:27: (found: an identifier)
libghdl: :56:36: '<=' is expected instead of "output"
libghdl: :56:42: ';' expected at end of signal assignment
libghdl: :56:42: (found: 'to')
libghdl: :56:43: unexpected token 'to' in a concurrent statement list
libghdl: :58:0: unexpected token 'begin' in a concurrent statement list
libghdl: :59:6: '==' is not the vhdl equality, replaced by '='
libghdl: :85:18: ':' expected after interface identifier
libghdl: :85:18: (found: an identifier)
libghdl: :85:23: ';' or ')' expected after interface
libghdl: :86:12: ':' expected after interface identifier
libghdl: :86:12: (found: an identifier)
libghdl: :86:18: ';' or ')' expected after interface
libghdl: :90:2: object class keyword such as 'variable' is expected
libghdl: :91:2: 'begin' is expected instead of "quantity"
libghdl: :91:11: '<=' is expected instead of "vout"
libghdl: :91:15: ';' expected at end of signal assignment
libghdl: :91:15: (found: an identifier)
libghdl: :91:23: '<=' is expected instead of "iout"
libghdl: :91:27: ';' expected at end of signal assignment
libghdl: :91:27: (found: an identifier)
libghdl: :91:36: '<=' is expected instead of "output"
libghdl: :91:42: ';' expected at end of signal assignment
libghdl: :91:42: (found: 'to')
libghdl: :91:43: unexpected token 'to' in a concurrent statement list
libghdl: :93:10: '<=' is expected instead of "vin_temp"
libghdl: :93:18: ';' expected at end of signal assignment
libghdl: :93:18: (found: ':')
libghdl: :93:19: unexpected token ':' in a concurrent statement list
libghdl: :94:1: unexpected token 'constant' in a concurrent statement list
libghdl: :95:1: unexpected token 'constant' in a concurrent statement list
libghdl: :96:1: unexpected token 'constant' in a concurrent statement list
libghdl: :97:1: unexpected token 'constant' in a concurrent statement list
libghdl: :98:0: unexpected token 'begin' in a concurrent statement list
libghdl: :99:10: '==' is not the vhdl equality, replaced by '='
libghdl: :100:6: '==' is not the vhdl equality, replaced by '='
libghdl: :100:6: '<=' is expected instead of '='
libghdl: :100:6: unexpected token '=' in a primary
libghdl: :114:11: ':' expected after interface identifier
libghdl: :114:11: (found: an identifier)
libghdl: :114:16: ';' or ')' expected after interface
libghdl: :115:11: ':' expected after interface identifier
libghdl: :115:11: (found: an identifier)
libghdl: :115:17: ';' or ')' expected after interface
libghdl: :119:3: object class keyword such as 'variable' is expected
libghdl: :120:3: 'begin' is expected instead of "quantity"
libghdl: :120:12: '<=' is expected instead of "vout"
libghdl: :120:16: ';' expected at end of signal assignment
libghdl: :120:16: (found: an identifier)
libghdl: :120:24: '<=' is expected instead of "iout"
libghdl: :120:28: ';' expected at end of signal assignment
libghdl: :120:28: (found: an identifier)
libghdl: :120:37: '<=' is expected instead of "output"
libghdl: :120:43: ';' expected at end of signal assignment
libghdl: :120:43: (found: 'to')
libghdl: :120:44: unexpected token 'to' in a concurrent statement list
libghdl: :121:1: unexpected token 'constant' in a concurrent statement list
libghdl: :122:0: unexpected token 'begin' in a concurrent statement list
libghdl: :123:21: if/use is an AMS-VHDL statement
libghdl: :124:7: '==' is not the vhdl equality, replaced by '='
libghdl: :124:7: '==' expected after expression
libghdl: :124:7: (found: '=')
libghdl: :124:7: unexpected token '=' in a primary
libghdl: :124:6: ';' is expected instead of '='
libghdl: :124:7: unexpected token '=' in a simultaneous statement list
libghdl: :126:7: '==' is not the vhdl equality, replaced by '='
libghdl: :126:7: '==' expected after expression
libghdl: :126:7: (found: '=')
libghdl: :126:7: unexpected token '=' in a primary
libghdl: :126:6: ';' is expected instead of '='
libghdl: :126:7: unexpected token '=' in a simultaneous statement list
libghdl: :128:7: '==' is not the vhdl equality, replaced by '='
libghdl: :128:7: '==' expected after expression
libghdl: :128:7: (found: '=')
libghdl: :128:7: unexpected token '=' in a primary
libghdl: :128:6: ';' is expected instead of '='
libghdl: :128:7: unexpected token '=' in a simultaneous statement list
libghdl: :130:7: '<=' is expected instead of 'on'
libghdl: :130:7: unexpected token 'on' in a primary
libghdl: :130:6: ';' expected at end of signal assignment
libghdl: :130:6: (found: 'on')
libghdl: :130:7: unexpected token 'on' in a concurrent statement list
libghdl: :145:17: ':' expected after interface identifier
libghdl: :145:17: (found: an identifier)
libghdl: :145:26: ';' or ')' expected after interface
libghdl: :146:17: ':' expected after interface identifier
libghdl: :146:17: (found: an identifier)
libghdl: :146:24: ';' or ')' expected after interface
libghdl: :147:17: ':' expected after interface identifier
libghdl: :147:17: (found: an identifier)
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd] 0:00:00.231721

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd'
libghdl processing time:  66.502 us
DOM translation time:    232.704 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_02a(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd':
      Entities:
        - Name: inline_02a
          File: inline_02a.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_02a.vhd
          Position: 37:13
          Entity: inline_02a
          Declared:
          Hierarchy:
          Statements:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/DC_Motor.vhd] 0:00:00.249935

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/DC_Motor.vhd'
DOM: Error raised in libghdl.
libghdl: :30:18: ':' expected after interface identifier
libghdl: :30:18: (found: an identifier)
libghdl: :30:20: interfaces must be separated by ';' (found ',')
libghdl: :31:18: ':' expected after interface identifier
libghdl: :31:18: (found: an identifier)
libghdl: :31:29: ';' or ')' expected after interface
libghdl: :38:2: object class keyword such as 'variable' is expected
libghdl: :39:2: 'begin' is expected instead of "quantity"
libghdl: :39:11: '<=' is expected instead of "w"
libghdl: :39:12: ';' expected at end of signal assignment
libghdl: :39:12: (found: an identifier)
libghdl: :39:20: '<=' is expected instead of "torq"
libghdl: :39:24: ';' expected at end of signal assignment
libghdl: :39:24: (found: an identifier)
libghdl: :39:33: '<=' is expected instead of "shaft_rotv"
libghdl: :39:43: ';' expected at end of signal assignment
libghdl: :39:43: (found: 'to')
libghdl: :39:44: unexpected token 'to' in a concurrent statement list
libghdl: :41:0: unexpected token 'begin' in a concurrent statement list
libghdl: :43:7: '==' is not the vhdl equality, replaced by '='
libghdl: :44:5: '==' is not the vhdl equality, replaced by '='
libghdl: :44:5: '<=' is expected instead of '='
libghdl: :44:5: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd] 0:00:00.246941

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:21: ';' or ')' expected after interface
libghdl: :27:18: ':' expected after interface identifier
libghdl: :27:18: (found: an identifier)
libghdl: :27:21: ';' or ')' expected after interface
libghdl: :38:2: object class keyword such as 'variable' is expected
libghdl: :40:2: 'begin' is expected instead of "quantity"
libghdl: :41:11: '<=' is expected instead of "i_b2"
libghdl: :41:15: ';' expected at end of signal assignment
libghdl: :41:15: (found: an identifier)
libghdl: :41:24: '<=' is expected instead of "tb"
libghdl: :41:26: ';' expected at end of signal assignment
libghdl: :41:26: (found: 'to')
libghdl: :41:27: unexpected token 'to' in a concurrent statement list
libghdl: :43:11: '<=' is expected instead of "i_b3"
libghdl: :43:15: ';' expected at end of signal assignment
libghdl: :43:15: (found: an identifier)
libghdl: :43:24: '<=' is expected instead of "tz"
libghdl: :43:26: ';' expected at end of signal assignment
libghdl: :43:26: (found: 'to')
libghdl: :43:27: unexpected token 'to' in a concurrent statement list
libghdl: :45:11: '<=' is expected instead of "i_b4"
libghdl: :45:15: ';' expected at end of signal assignment
libghdl: :45:15: (found: an identifier)
libghdl: :45:24: '<=' is expected instead of "tz"
libghdl: :45:26: ';' expected at end of signal assignment
libghdl: :45:26: (found: 'to')
libghdl: :45:27: unexpected token 'to' in a concurrent statement list
libghdl: :49:0: unexpected token 'begin' in a concurrent statement list
libghdl: :64:18: ':' expected after interface identifier
libghdl: :64:18: (found: an identifier)
libghdl: :64:20: interfaces must be separated by ';' (found ',')
libghdl: :83:2: object class keyword such as 'variable' is expected
libghdl: :87:2: 'begin' is expected instead of "terminal"
libghdl: :87:11: '<=' is expected instead of "t"
libghdl: :87:12: ';' expected at end of signal assignment
libghdl: :87:12: (found: ':')
libghdl: :87:13: unexpected token ':' in a concurrent statement list
libghdl: :89:11: '<=' is expected instead of "i_t1"
libghdl: :89:21: ';' expected at end of signal assignment
libghdl: :89:21: (found: an identifier)
libghdl: :89:30: '<=' is expected instead of "t"
libghdl: :89:31: ';' expected at end of signal assignment
libghdl: :89:31: (found: 'to')
libghdl: :89:32: unexpected token 'to' in a concurrent statement list
libghdl: :91:11: '<=' is expected instead of "i_t3"
libghdl: :91:15: ';' expected at end of signal assignment
libghdl: :91:15: (found: an identifier)
libghdl: :91:24: '<=' is expected instead of "ty"
libghdl: :91:26: ';' expected at end of signal assignment
libghdl: :91:26: (found: 'to')
libghdl: :91:27: unexpected token 'to' in a concurrent statement list
libghdl: :96:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd] 0:00:00.256977

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd'
libghdl processing time:  70.602 us
DOM translation time:    308.105 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_05a(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd':
      Entities:
        - Name: inline_05a
          File: inline_05a.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_05a.vhd
          Position: 25:13
          Entity: inline_05a
          Declared:
            - type domain_type is (........)
            - signal domain : domain_type := quiescent_domain
          Hierarchy:
          Statements:
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XFAIL test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd] 0:00:00.243466

Setup

Call

[gw1] linux -- Python 3.9.9 /opt/hostedtoolcache/Python/3.9.9/x64/bin/python

file = '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd'

    @mark.parametrize(
    	"file",
    	getVHDLSources()
    )
    @mark.xfail
    def test_AllVHDLSources(file):
>   	check_call(['ghdl-dom', 'pretty', '-f', str(file)], stderr=STDOUT)

TestDOM.py:25: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

popenargs = (['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd'],)
kwargs = {'stderr': -2}, retcode = 6
cmd = ['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd']

    def check_call(*popenargs, **kwargs):
        """Run command with arguments.  Wait for command to complete.  If
        the exit code was zero then return, otherwise raise
        CalledProcessError.  The CalledProcessError object will have the
        return code in the returncode attribute.
    
        The arguments are the same as for the call function.  Example:
    
        check_call(["ls", "-l"])
        """
        retcode = call(*popenargs, **kwargs)
        if retcode:
            cmd = kwargs.get("args")
            if cmd is None:
                cmd = popenargs[0]
>           raise CalledProcessError(retcode, cmd)
E           subprocess.CalledProcessError: Command '['ghdl-dom', 'pretty', '-f', '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd']' returned non-zero exit status 6.

/opt/hostedtoolcache/Python/3.9.9/x64/lib/python3.9/subprocess.py:373: CalledProcessError
Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 57
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 63
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 69
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 75
DOM: Unknown instantiation kind 'Selected_Name' in instantiation of label cpu_bus_monitor at /home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd:132:4.

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd] 0:00:00.254359

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:23: interfaces must be separated by ';' (found ',')
libghdl: :32:18: ':' expected after interface identifier
libghdl: :32:18: (found: an identifier)
libghdl: :32:23: interfaces must be separated by ';' (found ',')
libghdl: :39:18: ':' expected after interface identifier
libghdl: :39:18: (found: an identifier)
libghdl: :39:22: interfaces must be separated by ';' (found ',')
libghdl: :61:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd] 0:00:00.259934

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd'
DOM: Error raised in libghdl.
libghdl: :23:18: ':' expected after interface identifier
libghdl: :23:18: (found: an identifier)
libghdl: :23:22: interfaces must be separated by ';' (found ',')
libghdl: :38:18: ':' expected after interface identifier
libghdl: :38:18: (found: an identifier)
libghdl: :38:22: interfaces must be separated by ';' (found ',')
libghdl: :53:18: ':' expected after interface identifier
libghdl: :53:18: (found: an identifier)
libghdl: :53:21: interfaces must be separated by ';' (found ',')
libghdl: :54:18: ':' expected after interface identifier
libghdl: :54:18: (found: an identifier)
libghdl: :54:19: interfaces must be separated by ';' (found ',')
libghdl: :62:20: ':' expected after interface identifier
libghdl: :62:20: (found: an identifier)
libghdl: :62:24: interfaces must be separated by ';' (found ',')
libghdl: :66:20: ':' expected after interface identifier
libghdl: :66:20: (found: an identifier)
libghdl: :66:24: interfaces must be separated by ';' (found ',')
libghdl: :69:2: object class keyword such as 'variable' is expected
libghdl: :74:13: '<=' is expected instead of "clk_pulldown_drain"
libghdl: :74:31: ';' expected at end of signal assignment
libghdl: :74:31: (found: ':')
libghdl: :74:32: unexpected token ':' in a concurrent statement list
libghdl: :75:2: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd] 0:00:00.258536

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:22: interfaces must be separated by ';' (found ',')
libghdl: :33:2: object class keyword such as 'variable' is expected
libghdl: :34:2: 'begin' is expected instead of 'signal'
libghdl: :34:2: unexpected token 'signal' in a concurrent statement list
libghdl: :36:0: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd] 0:00:00.246767

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd'
libghdl processing time:  88.502 us
DOM translation time:    81.101 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - identical_devices
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: identical_devices
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd] 0:00:00.252047

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd'
DOM: Error raised in libghdl.
libghdl: :32:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd] 0:00:00.235686

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd'
libghdl processing time:  110.202 us
DOM translation time:    127.503 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - last_pass_spice
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: last_pass_spice
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd] 0:00:00.241762

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd'
DOM: Error raised in libghdl.
libghdl: :24:18: ':' expected after interface identifier
libghdl: :24:18: (found: an identifier)
libghdl: :24:23: interfaces must be separated by ';' (found ',')
libghdl: :31:2: object class keyword such as 'variable' is expected

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd] 0:00:00.238042

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd'
libghdl processing time:  111.802 us
DOM translation time:    599.411 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - DRAM_4M_by_4(chip_function)
      Packages:
      Configurations:
        - down_to_chips
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd':
      Entities:
        - Name: DRAM_4M_by_4
          File: down_to_chips.vhd
          Position: 22:7
          Generics:
          Ports:
            - a : in std_logic_vector(0 to 10)
            - d : inout std_logic_vector(0 to 3)
            - cs, we, ras, cas : in std_logic
          Declared:
          Statements:
          Architecures:
          - chip_function
      Architectures:
        - Name: chip_function
          File: down_to_chips.vhd
          Position: 29:13
          Entity: DRAM_4M_by_4
          Declared:
          Hierarchy:
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
        - Name: down_to_chips
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd] 0:00:00.231663

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd'
libghdl processing time:  65.001 us
DOM translation time:    53.201 us

Design:
  Libraries:
    - Name: pretty
      Entities:
      Packages:
      Configurations:
        - architectural
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd':
      Entities:
      Architectures:
      Packages:
      PackageBodies:
      Configurations:
        - Name: architectural
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd] 0:00:00.238917

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd'
DOM: Error raised in libghdl.
libghdl: :25:18: ':' expected after interface identifier
libghdl: :25:18: (found: an identifier)
libghdl: :25:20: interfaces must be separated by ';' (found ',')
libghdl: :36:18: ':' expected after interface identifier
libghdl: :36:18: (found: an identifier)
libghdl: :36:23: interfaces must be separated by ';' (found ',')
libghdl: :51:18: ':' expected after interface identifier
libghdl: :51:18: (found: an identifier)
libghdl: :51:25: ';' or ')' expected after interface
libghdl: :52:18: ':' expected after interface identifier
libghdl: :52:18: (found: an identifier)
libghdl: :52:33: ';' or ')' expected after interface
libghdl: :60:20: ':' expected after interface identifier
libghdl: :60:20: (found: an identifier)
libghdl: :60:22: interfaces must be separated by ';' (found ',')
libghdl: :64:20: ':' expected after interface identifier
libghdl: :64:20: (found: an identifier)
libghdl: :64:25: interfaces must be separated by ';' (found ',')
libghdl: :71:13: '<=' is expected instead of "led_anode"
libghdl: :71:22: ';' expected at end of signal assignment
libghdl: :71:22: (found: ':')
libghdl: :71:23: unexpected token ':' in a concurrent statement list
libghdl: :73:2: unexpected token 'begin' in a concurrent statement list

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd] 0:00:00.237745

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd'
libghdl processing time:  106.302 us
DOM translation time:    908.016 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_02(test)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd':
      Entities:
        - Name: inline_02
          File: inline_02.vhd
          Position: 22:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_02.vhd
          Position: 26:13
          Entity: inline_02
          Declared:
            - signal unbuffered_clock : std_logic
            - signal buffered_clock_array : std_logic_vector(0 to 7)
          Hierarchy:
            - clock_buffer_tree: entity work.fanout_tree
            - clock_gen: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd] 0:00:00.233402

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd'
[NOT IMPLEMENTED] Bit String Literal not supported yet
libghdl processing time:  235.804 us
DOM translation time:    2192.438 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - DRAM(empty)
        - memory_board(chip_level)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd':
      Entities:
        - Name: DRAM
          File: memory_board.vhd
          Position: 24:7
          Generics:
          Ports:
            - a : in std_logic_vector(0 to 10)
            - d : inout std_logic_vector(0 to 3)
            - cs, we, ras, cas : in std_logic
          Declared:
          Statements:
          Architecures:
          - empty
        - Name: memory_board
          File: memory_board.vhd
          Position: 40:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - chip_level
      Architectures:
        - Name: empty
          File: memory_board.vhd
          Position: 31:13
          Entity: DRAM
          Declared:
          Hierarchy:
          Statements:
            ...
        - Name: chip_level
          File: memory_board.vhd
          Position: 46:13
          Entity: memory_board
          Declared:
            - Component: DRAM
              Generics:
              Ports:
                - a : in std_logic_vector(0 to 10)
                - d : inout std_logic_vector(0 to 3)
                - cs, we, ras, cas : in std_logic
            - signal buffered_address : std_logic_vector(0 to 10)
            - signal DRAM_data : std_logic_vector(0 to 31)
            - signal bank_select : std_logic_vector(0 to 3)
            - signal buffered_we, buffered_ras, buffered_cas : std_logic
          Hierarchy:
            - bank_array: for bank_index in 0 to 3 generate
                - nibble_array: for nibble_index in 0 to 7 generate
                    - a_dram: component DRAM
          Statements:
            ...
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd] 0:00:00.240582

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd'
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Array_Subtype_Definition
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 48
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 49
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 50
[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: 'clock_gen') at line 59
libghdl processing time:  227.004 us
DOM translation time:    2557.445 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - graphics_engine(behavioral)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd':
      Entities:
        - Name: graphics_engine
          File: graphics_engine.vhd
          Position: 22:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - behavioral
      Architectures:
        - Name: behavioral
          File: graphics_engine.vhd
          Position: 28:13
          Entity: graphics_engine
          Declared:
            - type ???? is array(........) of .....
            - type ???? is array(........) of .....
            - signal p, transformed_p : point
            - signal a : transformation_matrix
            - signal clock : bit
          Hierarchy:
            - transform_stage: for i in 1 to 3 generate
                - cross_product_transform: process(...)
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl.vhd] 0:00:00.237881

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl.vhd'
DOM: Error raised in libghdl.
libghdl: :26:18: ':' expected after interface identifier
libghdl: :26:18: (found: an identifier)
libghdl: :26:19: interfaces must be separated by ';' (found ',')
libghdl: :33:2: object class keyword such as 'variable' is expected
libghdl: :34:2: 'begin' is expected instead of "quantity"
libghdl: :34:11: '<=' is expected instead of "v2"
libghdl: :34:13: ';' expected at end of signal assignment
libghdl: :34:13: (found: an identifier)
libghdl: :34:21: '<=' is expected instead of "i2"
libghdl: :34:23: ';' expected at end of signal assignment
libghdl: :34:23: (found: an identifier)
libghdl: :34:32: '<=' is expected instead of "c"
libghdl: :34:33: ';' expected at end of signal assignment
libghdl: :34:33: (found: 'to')
libghdl: :34:34: unexpected token 'to' in a concurrent statement list
libghdl: :35:11: '<=' is expected instead of "r1"
libghdl: :35:17: ';' expected at end of signal assignment
libghdl: :35:17: (found: ':')
libghdl: :35:18: unexpected token ':' in a concurrent statement list
libghdl: :37:0: unexpected token 'begin' in a concurrent statement list
libghdl: :39:8: a generate statement must have a label
libghdl: :40:7: '==' is not the vhdl equality, replaced by '='
libghdl: :40:7: '<=' is expected instead of '='
libghdl: :40:7: unexpected token '=' in a primary
libghdl: :41:7: '==' is not the vhdl equality, replaced by '='
libghdl: :41:7: '<=' is expected instead of '='
libghdl: :41:7: unexpected token '=' in a primary
libghdl: :42:15: end label for an unlabeled declaration or statement
libghdl: :45:7: '==' is not the vhdl equality, replaced by '='
libghdl: :45:7: '<=' is expected instead of '='
libghdl: :45:7: unexpected token '=' in a primary
libghdl: :46:7: '==' is not the vhdl equality, replaced by '='
libghdl: :46:7: '<=' is expected instead of '='
libghdl: :46:7: unexpected token '=' in a primary
libghdl: :49:5: '==' is not the vhdl equality, replaced by '='
libghdl: :49:5: '<=' is expected instead of '='
libghdl: :49:5: unexpected token '=' in a primary
libghdl: :50:5: '==' is not the vhdl equality, replaced by '='
libghdl: :50:5: '<=' is expected instead of '='
libghdl: :50:5: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd] 0:00:00.267805

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd'
libghdl processing time:  160.103 us
DOM translation time:    2049.236 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - buf(basic)
        - fanout_tree(recursive)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd':
      Entities:
        - Name: buf
          File: fanout_tree.vhd
          Position: 22:7
          Generics:
          Ports:
            - a : in std_logic
            - y : out std_logic
          Declared:
          Statements:
          Architecures:
          - basic
        - Name: fanout_tree
          File: fanout_tree.vhd
          Position: 39:7
          Generics:
            - height : in natural
          Ports:
            - input : in std_logic
            - output : out std_logic_vector(0 to 2**height - 1)
          Declared:
          Statements:
          Architecures:
          - recursive
      Architectures:
        - Name: basic
          File: fanout_tree.vhd
          Position: 27:13
          Entity: buf
          Declared:
          Hierarchy:
          Statements:
            ...
        - Name: recursive
          File: fanout_tree.vhd
          Position: 47:13
          Entity: fanout_tree
          Declared:
          Hierarchy:
            - degenerate_tree: if height = 0 generate
            - compound_tree: if height > 0 generate
                - buf_0: entity work.buf
                - subtree_0: entity work.fanout_tree
                - buf_1: entity work.buf
                - subtree_1: entity work.fanout_tree
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd] 0:00:00.240125

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd'
DOM: Error raised in libghdl.
libghdl: :29:18: ':' expected after interface identifier
libghdl: :29:18: (found: an identifier)
libghdl: :29:20: interfaces must be separated by ';' (found ',')
libghdl: :36:2: object class keyword such as 'variable' is expected
libghdl: :37:2: 'begin' is expected instead of 'signal'
libghdl: :37:2: unexpected token 'signal' in a concurrent statement list
libghdl: :39:0: unexpected token 'begin' in a concurrent statement list
libghdl: :41:17: a generate statement must have a label
libghdl: :43:62: if/use is an AMS-VHDL statement
libghdl: :44:9: '==' is not the vhdl equality, replaced by '='
libghdl: :44:9: '==' expected after expression
libghdl: :44:9: (found: '=')
libghdl: :44:9: unexpected token '=' in a primary
libghdl: :44:8: ';' is expected instead of '='
libghdl: :44:9: unexpected token '=' in a simultaneous statement list
libghdl: :46:9: '==' is not the vhdl equality, replaced by '='
libghdl: :46:9: '==' expected after expression
libghdl: :46:9: (found: '=')
libghdl: :46:9: unexpected token '=' in a primary
libghdl: :46:8: ';' is expected instead of '='
libghdl: :46:9: unexpected token '=' in a simultaneous statement list
libghdl: :58:15: end label for an unlabeled declaration or statement
libghdl: :62:6: '==' is not the vhdl equality, replaced by '='
libghdl: :62:6: '<=' is expected instead of '='
libghdl: :62:6: unexpected token '=' in a primary

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd] 0:00:00.245202

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd'
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 61
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 63
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 65
[NOT IMPLEMENTED] Variable assignment (label: 'None') at line 67
libghdl processing time:  256.005 us
DOM translation time:    5916.404 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - computer_system(block_level)
      Packages:
      Configurations:
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd':
      Entities:
        - Name: computer_system
          File: computer_system.vhd
          Position: 22:7
          Generics:
            - instrumented : in boolean := false
          Ports:
            - other_port : in bit := 0
          Declared:
          Statements:
          Architecures:
          - block_level
      Architectures:
        - Name: block_level
          File: computer_system.vhd
          Position: 35:13
          Entity: computer_system
          Declared:
            - signal clock : bit
            - signal mem_req : bit
            - signal ifetch : bit
            - signal write : bit
          Hierarchy:
            - instrumentation: if instrumented generate
                - access_monitor: process(...)
            - stimulus: process(...)
          Statements:
            ...
            ...
      Packages:
      PackageBodies:
      Configurations:
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd] 0:00:00.238442

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd'
DOM: Error raised in libghdl.
libghdl: :69:13: ':' expected after interface identifier
libghdl: :69:13: (found: an identifier)
libghdl: :69:15: interfaces must be separated by ';' (found ',')
libghdl: :80:2: object class keyword such as 'variable' is expected
libghdl: :84:52: if/use is an AMS-VHDL statement
libghdl: :85:6: '==' is not the vhdl equality, replaced by '='
libghdl: :85:6: '==' expected after expression
libghdl: :85:6: (found: '=')
libghdl: :85:6: unexpected token '=' in a primary
libghdl: :85:5: ';' is expected instead of '='
libghdl: :85:6: unexpected token '=' in a simultaneous statement list
libghdl: :87:8: '==' is not the vhdl equality, replaced by '='
libghdl: :87:8: '==' expected after expression
libghdl: :87:8: (found: '=')
libghdl: :87:8: unexpected token '=' in a primary
libghdl: :87:5: ';' is expected instead of '='
libghdl: :87:8: unexpected token '=' in a simultaneous statement list
libghdl: :95:2: object class keyword such as 'variable' is expected
libghdl: :99:52: if/use is an AMS-VHDL statement
libghdl: :100:6: '==' is not the vhdl equality, replaced by '='
libghdl: :100:6: '==' expected after expression
libghdl: :100:6: (found: '=')
libghdl: :100:6: unexpected token '=' in a primary
libghdl: :100:5: ';' is expected instead of '='
libghdl: :100:6: unexpected token '=' in a simultaneous statement list
libghdl: :102:8: '==' is not the vhdl equality, replaced by '='
libghdl: :102:8: '==' expected after expression
libghdl: :102:8: (found: '=')
libghdl: :102:8: unexpected token '=' in a primary
libghdl: :102:5: ';' is expected instead of '='
libghdl: :102:8: unexpected token '=' in a simultaneous statement list
libghdl: :151:18: ':' expected after interface identifier
libghdl: :151:18: (found: an identifier)
libghdl: :151:20: interfaces must be separated by ';' (found ',')
libghdl: :155:2: object class keyword such as 'variable' is expected
libghdl: :156:2: 'begin' is expected instead of "quantity"
libghdl: :156:11: '<=' is expected instead of "vc"
libghdl: :156:13: ';' expected at end of signal assignment
libghdl: :156:13: (found: ':')
libghdl: :156:14: unexpected token ':' in a concurrent statement list
libghdl: :157:0: unexpected token 'begin' in a concurrent statement list
libghdl: :158:52: if/use is an AMS-VHDL statement
libghdl: :159:7: '==' is not the vhdl equality, replaced by '='
libghdl: :159:7: '==' expected after expression
libghdl: :159:7: (found: '=')
libghdl: :159:7: unexpected token '=' in a primary
libghdl: :159:6: ';' is expected instead of '='
libghdl: :159:7: unexpected token '=' in a simultaneous statement list
libghdl: :160:6: '==' is not the vhdl equality, replaced by '='
libghdl: :160:6: '==' expected after expression
libghdl: :160:6: (found: '=')
libghdl: :160:6: unexpected token '=' in a primary
libghdl: :160:5: ';' is expected instead of '='
libghdl: :160:6: unexpected token '=' in a simultaneous statement list
libghdl: :162:7: '==' is not the vhdl equality, replaced by '='
libghdl: :162:7: '==' expected after expression
libghdl: :162:7: (found: '=')
libghdl: :162:7: unexpected token '=' in a primary
libghdl: :162:6: ';' is expected instead of '='
libghdl: :162:7: unexpected token '=' in a simultaneous statement list
libghdl: :163:6: '==' is not the vhdl equality, replaced by '='
libghdl: :163:6: '==' expected after expression
libghdl: :163:6: (found: '=')
libghdl: :163:6: unexpected token '=' in a primary
libghdl: :163:5: ';' is expected instead of '='
libghdl: :163:6: unexpected token '=' in a simultaneous statement list
libghdl: :222:13: ':' expected after interface identifier
libghdl: :222:13: (found: an identifier)
libghdl: :222:16: interfaces must be separated by ';' (found ',')
libghdl: :232:2: object class keyword such as 'variable' is expected
libghdl: :234:2: 'begin' is expected instead of "quantity"
libghdl: :234:11: '<=' is expected instead of "ac_spec"
libghdl: :234:18: ';' expected at end of signal assignment
libghdl: :234:18: (found: ':')
libghdl: :234:19: unexpected token ':' in a concurrent statement list
libghdl: :236:0: unexpected token 'begin' in a concurrent statement list
libghdl: :238:55: if/use is an AMS-VHDL statement
libghdl: :239:6: '==' is not the vhdl equality, replaced by '='
libghdl: :239:6: '==' expected after expression
libghdl: :239:6: (found: '=')
libghdl: :239:6: unexpected token '=' in a primary
libghdl: :239:5: ';' is expected instead of '='
libghdl: :239:6: unexpected token '=' in a simultaneous statement list
libghdl: :241:8: '==' is not the vhdl equality, replaced by '='
libghdl: :241:8: '==' expected after expression
libghdl: :241:8: (found: '=')
libghdl: :241:8: unexpected token '=' in a primary
libghdl: :241:5: ';' is expected instead of '='
libghdl: :241:8: unexpected token '=' in a simultaneous statement list
libghdl: :262:17: ':' expected after interface identifier
libghdl: :262:17: (found: an identifier)
libghdl: :262:18: interfaces must be separated by ';' (found ',')
libghdl: :267:2: object class keyword such as 'variable' is expected
libghdl: :268:2: 'begin' is expected instead of "quantity"
libghdl: :268:11: '<=' is expected instead of "v2"
libghdl: :268:13: ';' expected at end of signal assignment
libghdl: :268:13: (found: an identifier)
libghdl: :268:21: '<=' is expected instead of "i2"
libghdl: :268:23: ';' expected at end of signal assignment
libghdl: :268:23: (found: an identifier)
libghdl: :268:32: '<=' is expected instead of "c"
libghdl: :268:33: ';' expected at end of signal assignment
libghdl: :268:33: (found: 'to')
libghdl: :268:34: unexpected token 'to' in a concurrent statement list
libghdl: :269:11: '<=' is expected instead of "r1"
libghdl: :269:17: ';' expected at end of signal assignment
libghdl: :269:17: (found: ':')
libghdl: :269:18: unexpected token ':' in a concurrent statement list
libghdl: :270:0: unexpected token 'begin' in a concurrent statement list
libghdl: :271:22: if/use is an AMS-VHDL statement
libghdl: :272:9: '==' is not the vhdl equality, replaced by '='
libghdl: :272:9: '==' expected after expression
libghdl: :272:9: (found: '=')
libghdl: :272:9: unexpected token '=' in a primary
libghdl: :272:8: ';' is expected instead of '='
libghdl: :272:9: unexpected token '=' in a simultaneous statement list
libghdl: :273:9: '==' is not the vhdl equality, replaced by '='
libghdl: :273:9: '==' expected after expression
libghdl: :273:9: (found: '=')
libghdl: :273:9: unexpected token '=' in a primary
libghdl: :273:8: ';' is expected instead of '='
libghdl: :273:9: unexpected token '=' in a simultaneous statement list
libghdl: :0:0: error limit reached

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd] 0:00:00.251601

Setup

Call

Captured stdout call
================================================================================
                         pyGHDL.dom - Test Application                          
================================================================================
Parsing file '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd'
libghdl processing time:  110.702 us
DOM translation time:    487.709 us

Design:
  Libraries:
    - Name: pretty
      Entities:
        - inline_01(test)
      Packages:
      Configurations:
        - inline_01_test
      Contexts:
  Documents:
    - Path: '/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd':
      Entities:
        - Name: inline_01
          File: inline_01.vhd
          Position: 20:7
          Generics:
          Ports:
          Declared:
          Statements:
          Architecures:
          - test
      Architectures:
        - Name: test
          File: inline_01.vhd
          Position: 24:13
          Entity: inline_01
          Declared:
            - Component: computer_system
              Generics:
              Ports:
                - other_port : in bit := 0
          Hierarchy:
            - system_under_test: component computer_system
          Statements:
            ...
      Packages:
      PackageBodies:
      Configurations:
        - Name: inline_01_test
      Contexts:

Teardown

XPASS test_AllVHDLSources[/home/runner/work/extended-tests/extended-tests/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams.vhd] 0:00:00.229520

Setup

Call